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 One Page Computing - roll your own challenge 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 997
I'm not sure what you're seeing or why - perhaps you could show one or two worked examples?
Have you tried running the python emulator, or the javascript one? I think you see enough there to see what's going on.


Wed Sep 26, 2018 8:00 pm
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Joined: Sat Jun 16, 2018 2:51 am
Posts: 11
I get this:
Attachment:
predTable.png
predTable.png [ 10.44 KiB | Viewed 259 times ]

I'm trying to figure out how the architecture works from the verilog code...
In the python emulator, the line of code is still the same...
Code:
if (bool(pinvert) ^ bool(((pcarry or c) and (pzero or z)))):


Wed Sep 26, 2018 9:27 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 997
Hmm - have you noticed there's pcarry, which controls whether the predicate as a whole is sensitive to c, and pzero, which controls whether the predicate is sensitive to z? In the originally quoted table, "Carry pred" refers to the value of pcarry, and same for zero. That is, the columns are the value of the predicate control bit, not the cpu status bit.

As ever, there might be ways to improve the doc.

For the casual onlooker, the idea is that we can do a unconditional operation such as ld, or one only when z is set, with ld.z, or only when z is clear, with ld.nz, and so on. There's the always condition, the nop condition, and six others, which turns out to be quite powerful and flexible. More importantly for one-page computing, it's quite simple.

(We had another goal, of small implementation size, so simple in the implementation is good too.)

In later revisions of the architecture, we could take the 'nop' case and reuse it as an opcode bit, which means we get to double the operation count, with half of them predicated and half of them not.


Wed Sep 26, 2018 9:39 pm
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Joined: Sat Jun 16, 2018 2:51 am
Posts: 11
Ah I see. I was unaware of the instruction variation.

So, suppose you have instruction ld.z. pred_zero would be 1, pred_invert would be 0, and pred_carry would be 0. How will the predicate signal ever be high/true for the ld.z instruction? If,
Code:
predicate = pred_invert xor ( (pred_carry or flag_carry) and (pred_zero or flag_zero) )

Then the only way it can evaluate to true is if flag_carry is 1 ...

Thanks a lot for you time and patience!


Thu Sep 27, 2018 6:08 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 997
For whatever subtle reason, it seems the pred bits are negative logic, so for a ld.z you'd have pred_zero as 0, pred_carry as 1, and pred_invert as 0. I think that should work out.

Of course, at assembly level you don't worry about this. But of course the verilog, the assembler, the emulators, the monitor do all need to do it. (For at least some of these CPUs, we wrote (hoglet wrote) a single-stepping disassembling monitor which runs on the CPU, and has to understand enough to disassemble and single step. It was all rather interesting! See here
https://github.com/hoglet67/opc/blob/ma ... /monitor.s
and
https://github.com/hoglet67/opc/tree/master/include
)


Thu Sep 27, 2018 9:01 pm
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Joined: Sat Jun 16, 2018 2:51 am
Posts: 11
Ah ok! Thanks! I'll explore the programs as well =)


Thu Sep 27, 2018 10:54 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 997
There are some arithmetic libraries too - see the 'syslib' files in
https://github.com/revaldinho/opc/tree/master/bcpl


Fri Sep 28, 2018 7:40 am
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