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 24-bit word-oriented computing, some thoughts 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1146
Revaldinho did some analysis of quick syntheses (not optimal syntheses) of three OPC cores which, as it happens, have different word widths but also somewhat different instruction sets:

Quote:
Code:
      Bits  FFs  Slices  LUTs  MHz
OPC6   16    82    109    356   94
OPC8   24   130    121    415  172
OPC7   32   135    212    565  145


Attachment:
File comment: Comparing 3 OPC machines
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image(1).png [ 5.91 KiB | Viewed 130 times ]


Both OPC8 (24 bit) and 7 (32 bit) come out running at higher frequency than OPC6 (16 bit). There are a few reasons for this:
  • OPC6 had PUSH/POP which needed additional register updating (states and logic)
  • OPC7 and 8 both always use EAD so have minimum 2 cycle instructions (whereas OPC6 can have 1 cycle instructions) which simplifies the OPC7/8 state machine logic and possibly also some of the other register updating
  • OPC7 and 8 move the byte rotate/perm operations into EAD reducing the amount of muxing on the result of the ALU in EXEC

Comparing OPC7 and 8
  • OPC8 has no IN/OUT instructions which OPC7 had retained
  • OPC8 has a fixed format instruction with optional operand word whereas OPC7 had to detect two different types of single word instruction and deal with fields appropriately

And then of course OPC8 has a 24 bit word rather than a 32 bit one, although that doesn't really shorten the carry chain in add/subtract.

So, on the face of it OPC8 looks very good. Will be interesting to see if OPC6 has made up for that slower clock rate with better cycle efficiency by being able to skip EAD on some (definitely not all) instruction types when comparing the traces.


Beware: OPC6, 7 and 8 are named in order of invention, which is unfortunately not in order of word width. This can cause confusion, or at least, typos.

Edit: fixed a typo where OPC7 should have been OPC8. (!!)


Sat Apr 13, 2019 6:47 pm
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Joined: Fri Mar 22, 2019 8:03 am
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Location: Girona-Catalonia
Hi all,

Please, what do the acronyms "FFs", "Slices", "LUTs" and "EAD" stand for? I'm sure I know them all and it's only a language issue from my part (I'm not English native), so just expanding these acronyms to their complete words or providing a very simple definition will suffice. Sorry for briefly interfering the normal conversational flow, and thanks in advance!

Joan


Sat Apr 13, 2019 10:06 pm
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Location: Canada
FF’s stands for flip-flops which are also called registers. Whenever I see FF I think of a 74LS74 ‘D’ flip-flop.
Slices are a logic unit within an FPGA. An FPGA is composed of many slices. Slices typically contain multiple FF’s and LUT’s. Also similar are CLB’s which stands for configurable logic blocks.
LUT’s stands for look-up-table.
EA typically stands for effective-address. So EAD is a word associated with generating the effective address.

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Sun Apr 14, 2019 2:36 am
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Joined: Wed Jan 09, 2013 6:54 pm
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Indeed, FFs, slices and LUTs are all measures of the cost of the design in terms of resources on the FPGA. FFs are the state and LUTs are the logic, whereas each slice contains a number of both of those, and might be partially used. Different FPGA families have different LUT designs and different slice designs, so the counts of these may not be comparable across families, but within a family we can compare the cost of implementations by using these counts.

EAD is a pipeline stage: it's the stage which deals with the optional operand word, which either gives an Effective Address or gives some literal Data. (I think one could instead call it the Operand stage.) See this post for more on the pipeline:
viewtopic.php?p=3026#p3026

Edit: sorry about the obfuscation!

Edit: perhaps EAD is best described as a system state, not a pipeline stage.


Sun Apr 14, 2019 6:43 am
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Joined: Fri Mar 22, 2019 8:03 am
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Location: Girona-Catalonia
Thank you very much for the acronym definitions. It's now suddenly much clearer to me, and I understand what you are talking about. I appreciate it.


Sun Apr 14, 2019 8:54 pm
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