View unanswered posts | View active topics It is currently Mon Aug 19, 2019 11:57 am



Reply to topic  [ 3 posts ] 
 Instruction Level Parallelism - a historical survey 
Author Message
Online

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1225
Mark Smotherman surveys the history of instruction level parallelism, with some surprisingly early entrants, and a useful breakdown of the types of approach according to how late the interactions between instructions are resolved:
https://people.cs.clemson.edu/~mark/ilp.html

Earliest entries are from 1950, looking a bit like a pipelined machine and a microcoded machine.

So many architectures mentioned, and with links to many!

via 'ttlworks' posting over on 6502:
Ideas for a faster TTL CPU //6502 related


Sat Aug 10, 2019 12:04 pm
Profile

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 169
Location: Huntsville, AL
I have always enjoyed Mr. Smotherman's synopses of various topics in computer science/engineering. This particular synopsis pointed the way to some interesting approaches that I hope to study in more detail when I have some more time. I am especially interested in the details of the Cydra-5 computer.

A detailed description is provided in a journal. I'll have to wait until I can order that book from Amazon to get more details on this architecture.

_________________
Michael A.


Mon Aug 12, 2019 12:58 am
Profile
Online

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1225
Sounds like an interesting machine. Here's a brief description from a 1988 survey of minisupercomputers:
Quote:
Cydrome CYDRA 5: The CYDRA is a 'directed dataflow' very-long-instruction-word mini-supercomputer. It is very similar, in principle, to the architectures of FPS and Multiflow (Gentzsch, 1988a). In detail, however, there are many differences in the architectures and in the compilers. Directed dataflow technology is based on time-optimized scheduling of fine-grained parallel program execution. This implementation does as much scheduling as possible at compile time and relies on special hardware facilities to complete any remaining scheduling at run time. As a result, parallel speedup is maintained through conditional branches, regardless of the branch taken. A new address hashing scheme avoids performance degradation in accessing arrays of any size with any regular or irregular step size through data.


Mon Aug 12, 2019 7:12 am
Profile
Display posts from previous:  Sort by  
Reply to topic   [ 3 posts ] 

Who is online

Users browsing this forum: No registered users and 4 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
cron
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software