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 Instruction Level Parallelism - a historical survey 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1319
Mark Smotherman surveys the history of instruction level parallelism, with some surprisingly early entrants, and a useful breakdown of the types of approach according to how late the interactions between instructions are resolved:
https://people.cs.clemson.edu/~mark/ilp.html

Earliest entries are from 1950, looking a bit like a pipelined machine and a microcoded machine.

So many architectures mentioned, and with links to many!

via 'ttlworks' posting over on 6502:
Ideas for a faster TTL CPU //6502 related


Sat Aug 10, 2019 12:04 pm
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Joined: Wed Apr 24, 2013 9:40 pm
Posts: 179
Location: Huntsville, AL
I have always enjoyed Mr. Smotherman's synopses of various topics in computer science/engineering. This particular synopsis pointed the way to some interesting approaches that I hope to study in more detail when I have some more time. I am especially interested in the details of the Cydra-5 computer.

A detailed description is provided in a journal. I'll have to wait until I can order that book from Amazon to get more details on this architecture.

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Michael A.


Mon Aug 12, 2019 12:58 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1319
Sounds like an interesting machine. Here's a brief description from a 1988 survey of minisupercomputers:
Quote:
Cydrome CYDRA 5: The CYDRA is a 'directed dataflow' very-long-instruction-word mini-supercomputer. It is very similar, in principle, to the architectures of FPS and Multiflow (Gentzsch, 1988a). In detail, however, there are many differences in the architectures and in the compilers. Directed dataflow technology is based on time-optimized scheduling of fine-grained parallel program execution. This implementation does as much scheduling as possible at compile time and relies on special hardware facilities to complete any remaining scheduling at run time. As a result, parallel speedup is maintained through conditional branches, regardless of the branch taken. A new address hashing scheme avoids performance degradation in accessing arrays of any size with any regular or irregular step size through data.


Mon Aug 12, 2019 7:12 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1319
Here's a paper describing another machine mentioned in Mark's survey, the Astronautix ZS-1:
http://web.archive.org/web/200304160654 ... o_ZS-1.pdf

It's described as an MSI implementation of a mini-supercomputer, which separates two instruction streams which run in a decoupled fashion (an integer/address stream and a floating point stream) delivering one-third of a Cray XMP presumably at a much lower price. Edit: several nice diagrams within.

Edit: see also this tribute page
http://www.ricomputermuseum.org/Home/eq ... utics-zs-1


Tue Sep 10, 2019 9:16 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1319
There's a readable 1992 tech report from HP labs on ILP:
https://www.hpl.hp.com/techreports/92/HPL-92-132.pdf
(with over 200 citations for possible follow-up!)

Quote:
Instruction-level Parallelism CILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design. Several systems were built, and sold commercially, which pushed ILP far beyond where it had been before, both in terms of the amount of ILP offered and in the central role ILP played in the design of the system. By the end of the decade, advanced microprocessor design at all major CPU manufacturers had incorporated ILP, and new techniques for ILP have become a popular topic at academic conferences. This article provides an overview and historical perspective of the field of ILP and its development over the past three decades.


Tue Sep 10, 2019 9:46 am
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