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 New transistor design could revolutionise digital, analogue 
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 104
Hi All,

It's not everyday that you read about a fundamental new kind of transistor that could revolutionise the way we produce ICs.

Whilst Intel and their competitors are chasing 7nm technology with multi-billion investments in fabs and design teams, this new device is aiming to have appeal for the larger process sizes - in the 350nm to 1um range - which are generally the bread and butter of the smaller fabs.

Fundamentally the new process slashes weeks off IC manufacture by drastically reducing the number of different masks from dozens to just 4 to 8.

It could also allow regional universities to afford run student projects in IC design - and allow them to get their ICs back in a couple of weeks rather than 3 to 4 months.

The new device can give a whole new lease of life into these older process technologies, by allowing a three-fold increase in transistor (and logic) density, compared to CMOS or bipolar processes.

For example a 3 input NOR becomes a single bizen (bipolar-zener) transistor - rather than 4 for CMOS or 6 for TTL. (Apollo Guidance Computer - anyone?)

A D-type master-slave flip-flop becomes 8 transistors - down from the 22=8 to 35 typically needed for CMOS. Similar gains could be made for SRAM and other essential logic building blocks

Two articles from the electronics press describe the new device in good technical detail

https://www.electronicsweekly.com/news/ ... c-2019-10/

https://www.eetimes.com/document.asp?doc_id=1335216#


Fri Nov 08, 2019 12:52 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1299
Very interesting! I like the idea of cheap custom chips at small scale! A 1u process is good enough for so many hobby purposes.


Fri Nov 08, 2019 2:05 pm
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 104
Ed,

There are also patents (pending) for their Instantaneous Processor Unit (IPU) which sounds like it can process analogue signals without the complexity of ADC then digital processing then DAC.

The sort of application might include a LED lighting controller, power factor controller for switched mode power supply, a maximum power point tracker for a solar panel, or a phase driver for a brushless dc motor etc. Any device that needs a little intelligence plus power electronics.

This aim appears to put control/intelligence onto the same die as a power transistor stage, and this value added feature would allow the existing UK Semiconductor Fabs to find new markets for their spare capacity, and help their business from being undercut by lower cost Chinese fabs.

They (SFN) have a sister company called WaferTrain which is going to follow the model of some of the low cost pcb manufacturers (eg pcbTrain) where multiple customers put their designs onto a single wafer, which goes through the fab, is sawn up into individual die, and customers get their packaged silicon back in two weeks.

I think this would appeal to universities and hobbyists, low cost and quick turn-around.

A standards library of digital and analogue cells, and hopefully open-source tools to allow chip layouts to be completed quickly with minimum errors will complete the offering

This article explains a lot more of the background to their business


https://www.wafertrain.com/index.php/sf ... k&wallid=6


Fri Nov 08, 2019 2:24 pm
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