Welcome, Sheep64. I admire your positive and prolific attitude, and I always attempt to read and ruminate on your posts from beginning to end, with mixed success. Please keep the steady flow of ideas and products coming, and know that you have at least one fan.

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Indeed welcome, Sheep64.

You put yourself in a select group by reading the entirety of a forum - most impressive that you can also reference things you've read!

Hi everyone. I was born a bit too late to experience first-hand the world of 6502s and Z80s, my first exposure to computers being the Acorn Risc PCs we had in primary school, and the 486 we had at home. I remember coming across the homebrew CPU web ring as a kid in the early 2000s and being fascinated by all these weird and wonderful machines people were making. The web has changed quite a bit since then and it's nice to see the web ring is still going, and forums like this too.

I spent many years writing C for embedded systems (STM32 mostly) and doing a bit of electronics design. Also wrote quite a bit of Python on the back end and for things like test jigs. I've become a bit dismayed though with the complexity of modern software, and for me this CPU design hobby is a relief from it.

After a few failed attempts I've just got my first design working, called DIP-8. I'll make a thread about it shortly.

Welcome Kyle!

Hello Kyle, Welcome to the Forum. I'm looking forward to reading more about your DIP-8 project!

A new year, a new introduction. I'm often called JC for brevity. Started programming computers as a kid, end of the 1960's. My old-school experience, in somewhat chronological order: IBM-1130, CDC-6400, PDP-11, 6809, Z80. And on the software side: BCPL, Forth, C, Icon, Lua. Nowadays, I'm mostly working in C++ and Python on STM32 and MacOS (as a full-time hobby). I've dabbled a lot in electronics, mostly digital µC stuff, and built several retro-computers - from kits and my own designs. I'm a starter, not a finisher, so there are an infinite number of loose ends around my lab / playground. I'm interested in spanning the huge variety of computing technologies we have nowadays, from signal acquisition and logic gates to garbage-collected high-level languages and dataflow computing (not to mention neural nets and AI). Yep ... all of it (hence the loose ends).

Anyway. I've hooked up an iCE40 FPGA board from Olimex to an F723-Discovery board from STM, and find this setup fascinating in the range of things one can potentially do with this. The big hurdle for me right now is to get something non-trivial going with FPGA fabric. Beyond counting LEDs and generating a static VGA image, that is. For starters, perhaps a small CPU core to run SRAM memory tests? Even generating UART output is taxing my skills at the moment, a humbling experience for a software-oriented guy. I suppose part of the struggle is finding a good simulation / emulation context for this sort of development.

I've been reading posts on this forum lately, but there's a bit much to go through it all. I'd very much appreciate some tips to overcome these beginner's hurdles ...

Cheers,
Jean-Claude Wippler

Welcome!



I can totally relate to that. <looks guiltily around the graveyard of half-finished projects!>



Verilator and Icarus Verilog are both very well worth exploring for simulating verilog code, with the former making it very easy to integrate the simulated model within a C++ testbench.
GHDL is, likewise, a very useful VHDL simulator, and now supports synthesis well enough to be used as a plugin to the open-source toolchain, making it possible to synthesize VHDL projects with yosys / nextpnr.

Gtkwave is a nice waveform viewer, for examining the simulation results of the aforementioned tools.

Also, even though you're using a Lattice FPGA, it might be worth playing with the Xilinx toolchain "Vivado", since it has a pretty good simulator built-in. I use it if I need to simulate projects that contain both VHDL and Verilog in the same project, since the tools above aren't much help in that instance. Vivado is a *massive* download, though.

(If some simulation examples would be helpful, here's an example project which simulates my own CPU running a Dhrystone program, using GHDL: https://github.com/robinsonb5/EightThir ... /dhrystone
And here's a Verilator-based project to audition a number of different DAC designs in Verilog: https://github.com/robinsonb5/DACTests)

Welcome, JC! Please feel free to start an enquiry thread - either one big thread for all your adventures, or a number of individual threads. It's pretty quiet here, so your posts will be seen by everyone.

Thanks for the welcomes, @robinsonb5 and @BigEd. Good to see that this forum is still alive.

I've dabbled in verilator and iverilog a bit, a few years back. Will revisit, it does look like these are still valid options. I've also played with Altera's Quartus, and (less) with Xilinx's Vivado. Getting a permanent setup of the appropriate older versions of these tools going on Linux is on my todo list (I lost my old installs).

Will post in a new thread after reading up a bit more on this forum, once my questions and plans solidify a bit further.

I am developing an open-source FPGA, and (when income builds up) an OSHW meetup.

Github so far: https://github.com/RobinHodson/FPGA
I don't really have the time to update that, not helped by a slow PC.

That's not the main project page, but my main server bank has gone down, so here's my out-of-date backup documentation site: https://chipshed.org/svg

When my servers are up again, the previous documentation was: http://freedom.is/svg

This lag behind my current work is highly annoying.
I've been temporarily banned from LinkedIn, too, due to a bug on their end.

I need to reorganise my documentation (this is what the document outline in GitHub is about), but no tools exist with a new concept, so I'm having to write my own toolchain, including generating diagrams (which I like to animate).

I can't run Vivado either: My current Linux box is not up to the job.

So for now, I'm starting again with components on a breadboard: If I can't simulate it, I'll build it.

First test will be of the interconnect and a NOT gate in place of a LUT (to keep the component count down) in diode-relay logic,
then a larger design with a bit more indirect solid-state stuff.

I want to add JTAG to it, at first just with one test register (and an entirely separate test circuit), for compatibility with standard hardware tools, but here I hit a snag: While Verilog implementations of at least a TAP controller are around (ripped out of RISC-V) it isn't at all clear what that looks like as a schematic, and I'm not a fan of FF FSMs anyway. I tried asking on Quora, and got nowhere:
https://www.quora.com/unanswered/What-w ... DLs-please

My design is a fairly simple concept; I'm just running into a lot of issues, making it tangible.

A spinoff of this, is my coding CV, because it contains an online circuit simulator: https://chipshed.org/code


For now, I'm mainly here asking about JTAG/TAP.

Welcome!

Hello Everyone!

My name is Johan, and I'm a software programmer from Sweden.
I started by writing 6502 and 68000 assembly language back in the early '90s.

Recently, I have been geeking out reading about old and new ISAs, and I find it interesting that several are being discussed on this board.

Welcome! Please feel free to start a discussion thread if you find an interesting article or project!

Welcome! Two of my favorites, the 6502 and 68000. I got started in the '80s on Commodore PET computers. My most recent project is Q+ which attempts to be close to modern ISA.