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| 6502 instruction pipeline http://anycpu.org/forum/viewtopic.php?f=3&t=1075 |
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| Author: | spiff [ Tue Aug 29, 2023 9:59 pm ] |
| Post subject: | 6502 instruction pipeline |
In another thread... BigEd wrote: If you look at the tabulated state changes in this simulation you'll see that the Z flag is updated in cycle 9... This is the program: Code: LDX #$02 DEX BEQ skip DEX BEQ zero LDA #$7f skip: LDA #$44 zero: LDA #$67 NOP NOP Wow! I learned something new today, ehm tonight. Looking at the DEX instruction, the 6502 have a much deeper pipeline than I ever thought! I always assumed that cycle 1 was a fetch, and everything else happened in cycle 2, decode, execute, writeback. The above simulation show that even on a single byte instruction nothing is executing before cycle 3. Cycle 2 is decode, cycle 3 is execute, and cycle 4 is writeback. Fetch cycle and execute from previous instruction is overlapping as is the decode cycle and writeback from previous instruction. That double instruction fetch after single byte instructions always seemed strange (wasted) to me but now I understand why... It just took me 40 years. :) |
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| Author: | BigEd [ Wed Aug 30, 2023 2:47 pm ] |
| Post subject: | Re: 6502 instruction pipeline |
I think we all learned a lot when visual6502 came out! But some things can be figured out from observation and thinking hard. For reference, this is the thread you mention |
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