G'Day all,

I am designing a 16-Bit TTL CPU and was looking at building separate ROM, RAM and Stack Pointer memory spaces. The SP register and associated Stack RAM separate to the normal User accessible RAM. The CPU design is geared around doing a lot of parallel operations and the idea I had to allow stack operations to be independent of Instruction fetchs and RD/WR operations on RAM.

Why? - The idea being that you only need to do PUSH and POP operations and by using a separate bus between the registers and the SP unit you can free the address/data bus connecting the ROM or RAM to do other tasks in parallel.

The instruction set would include:

- RSP - Reset SP (resets back to 0000 or FFFF depending on which direction you want to PUSH/POP).
- LDSP - Load SP into a specific Register
- STSP - Store Register into the SP counter.
- and obviously PUSH & POP


Can anyone see a case where this would not work?

Sid