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 Stack Memory and User RAM 
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Joined: Wed Mar 26, 2025 9:50 pm
Posts: 6
G'Day all,

I am designing a 16-Bit TTL CPU and was looking at building separate ROM, RAM and Stack Pointer memory spaces. The SP register and associated Stack RAM separate to the normal User accessible RAM. The CPU design is geared around doing a lot of parallel operations and the idea I had to allow stack operations to be independent of Instruction fetchs and RD/WR operations on RAM.

Why? - The idea being that you only need to do PUSH and POP operations and by using a separate bus between the registers and the SP unit you can free the address/data bus connecting the ROM or RAM to do other tasks in parallel.

The instruction set would include:

- RSP - Reset SP (resets back to 0000 or FFFF depending on which direction you want to PUSH/POP).
- LDSP - Load SP into a specific Register
- STSP - Store Register into the SP counter.
- and obviously PUSH & POP


Can anyone see a case where this would not work?

Sid


Fri Apr 17, 2026 3:54 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1883
I'm sure you can make a distinct space for a stack work - it reminds me a bit of the simplest micros where there's a hardware stack of very finite depth for return addresses.

I note that you're thinking of using this stack space also for data. At which point, I wonder, because conventionally it's possible to do stack-relative addressing (on the 6502 one uses TSX and indexing from 0100+base.) And in Forth and other stack-based languages we see operations like SWAP. So, more is accessible than just the top of the stack. That doesn't stop the machine from being general purpose, but it might be worth thinking about.


Sat Apr 18, 2026 12:13 pm

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2505
Location: Canada
Looks good so far. I agree with BigEd, some sort of stack relative addressing would be good. Also, one may want to be able to add/subtract directly with the SP register. Sometimes values are pushed on the stack, but they are not popped. Instead, a value is added to the SP. I would be inclined to have the SP operate like any other register so that there does not need to be distinct LDSP / STSP instructions. Something like a general purpose LDREG / STREG (most often called MOVE) that can handle any register might work.

Usually loads and stores refer to memory operations and register transfer operations are called moves.

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Robert Finch http://www.finitron.ca


Wed Apr 22, 2026 5:28 pm WWW
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