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 BOOM - a high performance RISC-V implementation 
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Earlier this year, Rob said
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I found the BOOM processor project on the web. https://github.com/ucb-bar/riscv-boom which I started to study. It's an Out-of-order RISCV variant. RISCV has a number of features that make an OOO machine more manageable to implement.

and I was looking through some materials on it recently. I think there might be a lot to learn from this machine.
Image
There's more info at the "more info" section of the repository:
https://github.com/ucb-bar/riscv-boom#t ... -processor
Quote:
This is the source repository for the RV64G RISC-V superscalar Berkeley Out-of-Order Machine (BOOM), written in the Chisel hardware construction language. BOOM is a synthesizable core that targets ASIC processes. It can run on an FPGA (50 MHz on a zc706), but optimizing it to be an FPGA soft-core is a non-goal.

(A custom silicon implementation should hit 1.5GHz - the FPGA is slow because it can't retime the FPU)

Perhaps most accessible is a PDF explaining the implementation, at
https://riscv.org/wp-content/uploads/20 ... 3-BOOM.pdf
It's a parameterised superscalar microarchitecture, so we can see the size cost of moving up from dual-issue to quad-issue. (Maybe 20% more performance for 50% extra area.) It's 10k lines of code and took 4 person-years to get this far.


Sun Dec 11, 2016 4:06 pm
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It looks like an interesting machine. But getting an environment setup for Windows could be a challenge.
It’s still a good read if one can get used to the Scala / Chisel language. I learned a little bit from it.

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Mon Dec 12, 2016 6:33 am
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(I get the impression from elsewhere that the new Ubuntu-style shell in Windows 10 works very much like an Ubuntu command line with ubuntu package management. But I don't run Windows so I can't vouch for it personally.)

I do like the idea, in principle, of a new approach to HDL - both verilog and VHDL seem pretty awful, but they are standard. I haven't yet got an opinion on Chisel but it seems to have the right bullet points.


Mon Dec 12, 2016 7:04 am
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Just to add, there's a paper justifying the yet-another-instruction-set-architecture which includes an interesting critique of pre-existing ISAs:
https://people.eecs.berkeley.edu/~krste ... 2016-1.pdf


Mon Dec 12, 2016 5:01 pm
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At the opposite end of the spectrum, we find PicoRV32, a minimal 32-bit RISC-V implementation
- Small (750-2000 LUTs in 7-Series Xilinx Architecture)
- High fmax (250-450 MHz on 7-Series Xilinx FPGAs)

Is that maybe even smaller than Arlet's 6502?? It isn't far off, I think.

(Part of the point of RISC-V is that it describes a family of related, and in some ways compatible, ISAs, from 32 bit embedded to 128 bit full-on. Extensions such as floating point and compressed instruction set are defined but optional.)

(There's an efficient 128-bit emulator written by the wizard Fabrice Bellard, available in C and in-browser, running a small 64-bit Linux. With a couple of tweaks I was able to build and run it on OSX. It's MIT-licensed.)


Wed Dec 21, 2016 10:20 pm
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PicoRV is well done, bound to be useful if a high fmax is present. While PicoRV has a high fmax, I think it’s a non-overlapped pipeline and takes about 5-6 clock cycles to execute an instruction. In some cases a high fmax isn’t needed and one can get better performance out of a lower fmax with an overlapped pipeline.

Artlet’s core is slightly smaller (about 600LUTs IIRC). Artlet also has a small RISC core operating at 100MHz I think.

A couple of things I don’t like about RISC-V: lack of indexed addressing mode. A third register read port would be useful for some instructions (multiplex, mac, cas, indexed addressing). Basic RISC-V has a fixed position for all register ports but some of the extensions require the register port fields to be moved around anyways. It’s true that adding an additional port would likely lower the fmax a bit, but one gains a more powerful instruction set. I don’t like the way extended constants are handled. The instruction encoding looks complex with a two or three level opcode-funct3+. (It’s actually fairly easy to get used to though). I’d prefer more registers (64) over a separate floating point regfile for a larger system.
Still a superb architecture, and if mimicry is a sign of greatness… (I’ve coded a RISC-V compatible myself).

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Thu Dec 22, 2016 5:55 am
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My small RISC core is 387 LUTs without the barrel shifter. The 6502 core has 403 LUTs. Both targeting Spartan 6. I'm not sure how much of a difference there is between that and 7-series.


Thu Dec 22, 2016 7:40 am
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It would be interesting to hear about your RISC-V compatible, Rob.

And, Arlet, I either missed or have (shamefully) forgotten your x18-32 RISC core!
https://github.com/Arlet/x18-32


Thu Dec 22, 2016 8:42 am
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It's the core processor for the NoC project.
http://anycpu.org/forum/viewtopic.php?f=13&t=281#p1996
The simulation problem hasn't been figured out yet. And the core no longer works in the FPGA. It was running at 75MHz at one point, but since has been made larger and more complex, so the last working run was at 25MHz.
Some 64 bit instructions were added to the RISC-V base in order to support 32 bit constants directly. Whether it takes 2-3 clock cycles and instructions to use a 32 bit constant or a slightly lower fmax with single cycle constants makes little difference to performance.

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Thu Dec 22, 2016 5:49 pm
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Ah, thanks. Sorry to hear about the bit-rot.


Thu Dec 22, 2016 6:03 pm
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