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GRVI Phalanx - 500 very small RISC-V CPUs on an FPGA http://anycpu.org/forum/viewtopic.php?f=3&t=346 |
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Author: | BigEd [ Thu Dec 22, 2016 10:51 am ] |
Post subject: | GRVI Phalanx - 500 very small RISC-V CPUs on an FPGA |
From Hacker News: Quote: Jan Gray stuffed 400 RISC-V cores into a Xilinx Kintex UltraScale KU040 FPGA http://fpga.org/grvi-phalanx/ Slides: http://fpga.org/wp-content/uploads/2016 ... rkshop.pdf Web: http://fpga.org/grvi-phalanx/ Quote: GRVI is an FPGA-efficient RISC-V RV32I soft processor core, hand technology mapped and floorplanned for best performance/area as a processing element (PE) in a parallel processor. GRVI implements a 2 or 3 stage single issue pipeline, typically consumes 320 6-LUTS in a Xilinx UltraScale FPGA, and currently runs at 300-375 MHz in a Kintex UltraScale Quote: GRVI (“Groovy”) Gray Research RISC-V RV*I • Purpose: efficient parallel processing element. • Scalar, 2-3 stage pipeline RV32I+- + MUL/Hopt – 300-375 MHz (KU-2), 1.3-1.6? CPI – ~320 6-LUTs – ~1 “MIPS”/LUT It's not quite a conformant RISC-V - some bits missing, some extra. But 320 LUTs is pretty good. Attachment: Compute-Cluster.png [ 75.49 KiB | Viewed 3859 times ] Attachment: Torus-Network-On-Chip.png [ 65.81 KiB | Viewed 3859 times ] |
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