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The T9000 transputer [launched in 1991] integrates a complete computer in a single VLSI chip of over 2 million transistors. It contains 3 major subsysytems: a pipelined superscalar processor, a communications processor and a 16kbyte fully associative cache. In this paper we discuss some of the issues arising in the design of the T9000
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http://web.archive.org/web/201306040441 ... mos/T9000/where you'll find more documents - fear not, the *.doc files are actually plain text.
On the launch:
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Last week, Inmos added information to the promise, when Pearson and his team detailed the 50-MHz, 2 million-transistor device, boasting 10-times performance improvement while maintaining binary compatibility with its predecessors, the T400 and T800. At last week's disclosures Inmos was showing only subsystem-level silicon.
The sheer performance of the part--which peaks at 200 native Mips, according to Inmos simulations--could be enough to attract attention from the 32-bit market. But to achieve the performance, Inmos is resorting to a three-level-metal, l-micron CMOS process using Tungsten plugs, yielding a transistor density of 10,000 transistors/mm2 on a 180-mm2 die--a challenge to even the most seasoned CMOS vendor.
(The only other triple-metal 32-bit microprocessor that is currently known to be on the drawing board is Intel's 100MHz 486, which was presented in a technical paper at this year's International Solid-State Circuits Conference.)
You can read the technical paper online
here.
That's an overview - there's a Q&A which covers something of the microarchitectural level
here.
Nearby, I wrote this mini-rant:
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As an anecdote, the T9000 project was a disaster. It was broadly architected, and then the design was handled by half a dozen teams of half a dozen people each. All the teams proceeded bottom up, and were not especially experienced. The management was inexperienced too. Each of the component parts had a unique design style and many cell libraries were used. Communication between the parts was one failure point. Timing closure within some parts was near impossible - scratch that, timing analysis was near impossible - and timing between parts was another failure point. We went through at least 8 revisions. The initial vision might have been 50MHz, the target was reduced to 30MHz and I think more, and when the thing eventually almost worked it was 10MHz or less, and several years late. It was much larger than it needed to be for the price point, and at various points was too large for the package and too large for the photoreduction optics.
The Bristol part of Inmos/ST sort of recovered, or at least survived - the previous generation of transputers was re-implemented mainly by the younger elements of the team, to suit a more modern work flow and to live as SoCs in set top boxes. That was successful for some years. Many of the older elements of the (UK) team made a mass exodus to Sun (in the US) and made quite an impact on future SPARC offerings. Within ST, another ambitious CPU architecture was architected, designed, implemented and, finally, cancelled just at the point of getting working first silicon. That didn't get to market although there might be technical presentations about it. Part way through that endeavour there was a second exodus to Sun.
(There was another story running in parallel to this: Inmos unexpectedly hit gold when their colour look-up chips were taken up in some PC standard. There was then a growing graphics business, the other half of the Bristol activity, which amongst other things helped a new outfit called Nvidia make their first silicon. That was a case of the student overtaking the master, writ very large - ST's graphics business ended up closing while Nvidia went on to drive all their competitors into the ground.)
