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 Inmos' T9000 transputer project 
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Joined: Wed Jan 09, 2013 6:54 pm
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The T9000 transputer [launched in 1991] integrates a complete computer in a single VLSI chip of over 2 million transistors. It contains 3 major subsysytems: a pipelined superscalar processor, a communications processor and a 16kbyte fully associative cache. In this paper we discuss some of the issues arising in the design of the T9000

- http://web.archive.org/web/201306040441 ... mos/T9000/
where you'll find more documents - fear not, the *.doc files are actually plain text.

On the launch:
Quote:
Last week, Inmos added information to the promise, when Pearson and his team detailed the 50-MHz, 2 million-transistor device, boasting 10-times performance improvement while maintaining binary compatibility with its predecessors, the T400 and T800. At last week's disclosures Inmos was showing only subsystem-level silicon.

The sheer performance of the part--which peaks at 200 native Mips, according to Inmos simulations--could be enough to attract attention from the 32-bit market. But to achieve the performance, Inmos is resorting to a three-level-metal, l-micron CMOS process using Tungsten plugs, yielding a transistor density of 10,000 transistors/mm2 on a 180-mm2 die--a challenge to even the most seasoned CMOS vendor.

(The only other triple-metal 32-bit microprocessor that is currently known to be on the drawing board is Intel's 100MHz 486, which was presented in a technical paper at this year's International Solid-State Circuits Conference.)


You can read the technical paper online here.

That's an overview - there's a Q&A which covers something of the microarchitectural level here.

Nearby, I wrote this mini-rant:
Quote:
As an anecdote, the T9000 project was a disaster. It was broadly architected, and then the design was handled by half a dozen teams of half a dozen people each. All the teams proceeded bottom up, and were not especially experienced. The management was inexperienced too. Each of the component parts had a unique design style and many cell libraries were used. Communication between the parts was one failure point. Timing closure within some parts was near impossible - scratch that, timing analysis was near impossible - and timing between parts was another failure point. We went through at least 8 revisions. The initial vision might have been 50MHz, the target was reduced to 30MHz and I think more, and when the thing eventually almost worked it was 10MHz or less, and several years late. It was much larger than it needed to be for the price point, and at various points was too large for the package and too large for the photoreduction optics.


The Bristol part of Inmos/ST sort of recovered, or at least survived - the previous generation of transputers was re-implemented mainly by the younger elements of the team, to suit a more modern work flow and to live as SoCs in set top boxes. That was successful for some years. Many of the older elements of the (UK) team made a mass exodus to Sun (in the US) and made quite an impact on future SPARC offerings. Within ST, another ambitious CPU architecture was architected, designed, implemented and, finally, cancelled just at the point of getting working first silicon. That didn't get to market although there might be technical presentations about it. Part way through that endeavour there was a second exodus to Sun.

(There was another story running in parallel to this: Inmos unexpectedly hit gold when their colour look-up chips were taken up in some PC standard. There was then a growing graphics business, the other half of the Bristol activity, which amongst other things helped a new outfit called Nvidia make their first silicon. That was a case of the student overtaking the master, writ very large - ST's graphics business ended up closing while Nvidia went on to drive all their competitors into the ground.)


Tue Jan 10, 2017 7:06 pm
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BigEd wrote:
(There was another story running in parallel to this: Inmos unexpectedly hit gold when their colour look-up chips were taken up in some PC standard. There was then a growing graphics business, the other half of the Bristol activity, which amongst other things helped a new outfit called Nvidia make their first silicon. That was a case of the student overtaking the master, writ very large - ST's graphics business ended up closing while Nvidia went on to drive all their competitors into the ground.)
There's an Inmos G364 chip in the Olivetty M700-10 (I own one), the 700-10 is an implementation of Microsoft's 'Jazz' MIPS computer reference design. Another instance (also with the Inmos video) is the MIPS Magnum. As for Nvidia, I'm not sure why this isn't mentioned on Wikipedia, but the boost came out of SGI (Silicon Graphics) originally: EE Times: SGI graphics team moves to Nvidia. SGI had their Reality Engine.. I remember spinning 3D fighter airplanes etc. from the mid-nineties. And the team behind that is what went to Nvidia. History is full of similar stuff.. the Canadian 'Arrow' fighter was choke full of advanced technology (e.g. fly by wire, with feedback) in 1958-60. When the company was dissolved for political reasons, some of the people moved to the US, ending up working with Apollo, and another team moved to Europe to work with what became Concorde (which, incidentally, has a lot of its looks from the Arrow).


Wed Jan 11, 2017 8:58 am
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Interesting! The free flow of engineers is one of the merits of having local critical mass - Fairchild and the valley being the obvious example, but in my time both Bristol and Cambridge in the UK have their local ecosystems, and to some extent the M4 corridor too.

There are a couple of very interesting retrospectives from Iann Barron on Inmos - how the funding came and went, how the American subsidiary interacted with the UK parent (badly) and how the memory business, intended as a seed business for the transputer, got a life of its own.
http://www.cs.man.ac.uk/CCS/res/res32.htm#c
http://www.cs.man.ac.uk/CCS/res/res33.htm#c
Quote:
Going back to the transputer itself, we had two technical gurus, David May and Robert Milne. They were just like chalk and cheese - completely different in their approaches. Robert was substantially more clever than David, and David's quite clever enough.


Wed Jan 11, 2017 11:44 am
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I found this in the second article:
Quote:
The other product was the second test chip we had made for the transputer. We persuaded IBM to use this as their next generation graphic chip, and it became embedded in the PC as the SVGA standard. Some of the oddities in the present Windows operating system stem directly from the way this chip was designed to work with the transputer.
(I added the bold part).


Wed Jan 11, 2017 3:59 pm
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A little bit more detail on the T9000 aka T9.

Micro architecture diagram:
Attachment:
T9000-arch.png
T9000-arch.png [ 63.16 KiB | Viewed 2096 times ]


This comes from a May 93 paper, assessing the performance of the Rev C part - still by no means fully functioning, and comparing this 10MHz offering with the existing 25MHz T805. It doesn't look terribly good although they are optimistic. The paper has interesting notes about code sequences and performance.
As PDF. Original here, in compressed PostScript.

Quote:
The now available version T9000ะก of the processor has still limited functionality and is running with a reduced clock speed of only 10 MHz. At present it is able to reach a peak performance of 40 Mips and 3.33 MFlops.

The final version of the T9000 transputer was announced to run with a clock speed of 50MHz. It should provide a peak performance of 200 Mips and 25 MFlops.
from T9000 - A Preliminary Evaluation of Arithmetic Performance by G. Bader* and B. Przywara

Here's their diagram of the processor pipeline:
Attachment:
T9000-CPU-pipeline.png
T9000-CPU-pipeline.png [ 125.23 KiB | Viewed 2096 times ]


As you see, it's pipelined and superscalar. And with a serious amount of on-chip cache, for the time.


Thu Feb 23, 2017 11:13 am
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