View unanswered posts | View active topics It is currently Wed Oct 23, 2019 11:11 pm



Reply to topic  [ 1 post ] 
 NEC's V60 micro - 32 bits, CISC 
Author Message

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1284
.
This micro seemed a bit interesting - the instruction set apparently bears some relationship to their 36 bit mainframes. It has 'abundant' 32 bit registers (32 of them), is 32 bits on the inside but has only 16 bit external databus. I wonder how it compares to NatSemi's 32k micro. Some models were also able to execute V20/V30 code (which is 8088/8086 as far as I can tell.) Launched in 1986 at 16MHz.

Here's Wikipedia, for what it's worth:
https://en.wikipedia.org/wiki/NEC_V60
"Its manual describes them as mainframe-computer-based fully orthogonal instruction set, in other words, Complex Instruction Set Computer, which comprises; non-uniform length instructions, memory-to-memory operations including string manipulation, and fairly complex operand addressing schemes"
"It had a six-stage pipeline, built-in memory management unit and floating-point arithmetic. It was manufactured in 1.5 μm on a two-layer aluminium metal CMOS process using 375,000 transistors on a 13.9 × 13.8 mm2 die. It operated at 5 V and was initially packaged in a 68-pin PGA. The first version ran at 16 MHz and attained 3.5 MIPS. Its sample price at launch was set to ¥100,000 ($588.23). It entered full-scale production in August 1986."
"Paul Vixie described it as "a very VAX-ish arch""

Here's the model in MAME:
https://github.com/mamedev/mame/blob/ma ... 60/v60.cpp

which has this comment block:
Quote:
uPD70615 (V60)
Features:
- Virtual memory (paging method)
- Level protection architecture - 4-level hierarchical protection function
for system multi-programming.
- Abundant general registers - Thirty two 32-bit general registers for
optimizing compiler
- Refined instruction set - 2-address method: Arbitrary addressing mode
can be used independently for source operand and destination operand.
- Abundant address modes and data types - Auto increment/decrement mode
for string process, and memory indirect addressing for pointer operation
- High cost-to performance chip
- No multiprocessor system - no FRM function for increasing system
reliability using two or more processors.
- No V20/V30 simulation mode
Address bus: 24 bits
Data bus: 16 bits
Memory space: 4G bytes
Operating frequency: 16 MHz
Package: 120-pin QFP


Fri Oct 11, 2019 4:37 pm
Profile
Display posts from previous:  Sort by  
Reply to topic   [ 1 post ] 

Who is online

Users browsing this forum: No registered users and 1 guest


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
cron
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software