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 8 bit CPU challenge 
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Joined: Sat Aug 22, 2015 6:26 am
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I was working with Xilinx ISE (version 13 or so), and I didtn't find a way to constrain the size, but it did have option to optimize for speed vs area. Setting it to area made the result somewhat smaller. State machines were gray-coded instead of one-hot, for instance.


Wed May 10, 2017 11:23 am
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BTW Arlet, are your developments available to see somewhere, or you keeping it private for now?


Wed May 10, 2017 11:26 am
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Not published yet, but I could start a github repository with work in progress.


Wed May 10, 2017 11:32 am
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That would be great!


Wed May 10, 2017 11:35 am
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I spent last weekend working on the design, working in one window with editor + verilator to check the functionality, while I had ISE open in other window to check the slice progress. The source happened to be open in ISE editor as well, and at some point I saved it from there, and it replaced my source with a really old version, and I lost all my progress that I made.

I've been working on restoring the work, but since I didn't remember all the details, I had to reinvent some things, and they turned out differently.


Wed May 10, 2017 11:40 am
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Ouch.

I notice the redoubtable Eric Smith has a CDP1802 (COSMAC) core in VHDL - that's a contemporary (mid-70s) offering, has lots of registers and on-board DMA. Would be interesting to see how compact it could be.


Wed May 10, 2017 11:49 am
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robfinch wrote:
Did some coding / design for a 6800 like CPU, but it's up to 100 slices already and it's not even half done. Got jumps, call, and branches coded but no ALU operations. My original 6502 core was about 200 slices (800LUTs) IIRC.
Tempted to start the 8,400 slice challenge. 1/4 of a xc7a200. (DSD9 fits into this I think, with 80 bit FPU).
Could we have three challenges ? big, medium, and small ?

If you want to start a bigger challenge, go ahead, but I don't think I'll ever make something that would require 8400 slices :)


Wed May 10, 2017 11:52 am
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BigEd wrote:
I notice the redoubtable Eric Smith has a CDP1802 (COSMAC) core in VHDL - that's a contemporary (mid-70s) offering, has lots of registers and on-board DMA. Would be interesting to see how compact it could be.

Can you see if it meets the 128 slice requirement ? Would be interesting to compare it to other designs, even if you didn't write it yourself.


Wed May 10, 2017 11:58 am
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If the tools can put a design into a smaller area, the timing of the design may be affected. In some cases a smaller PLD can be used but the timing will not be as good (with a congested design) as if a larger one was used.
Quote:
might be somewhere between XC95216 and XC95288 in terms of complexity

I just looked these parts up and noticed they are marked for obsolesce.
Quote:
Oddly enough, I don't see a very very small FPGA offering from Xilinx. Or, is there a way to push an FPGA design into a small corner?

It's possible to floorplan an FPGA design to place it into a compact area. One could use one corner of the FPGA provided the resources used in the design are all available in that one corner. (Clock blocks, block ram resources, memory controllers). I'm guessing one might only want to use a fraction of the pins available in some design. Pins could be selected to make PCB routing easier.

I think very very small FPGA's may not be offered because of transistors available with modern process. I wonder if manufacturing limits come into play here. Too few transistors used resulting in too small of a die ?

I use GitHub to back stuff that I would freak about if the hard-drive crashed, so It's mostly work-in-progress.

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Wed May 10, 2017 11:59 am
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Indeed, I wouldn't intend to use the larger 95xx's as components, just as a convenient synthesis target.

The floorplanning idea is a good one: a quarter of the smallest Spartan 6, the XC6SLX4, would be 150 slices, and there's a fair chance a quarter will contain all the bits needed.


Wed May 10, 2017 12:05 pm
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Quote:
If you want to start a bigger challenge, go ahead, but I don't think I'll ever make something that would require 8400 slices


Be brazen.
Even simple designs can use a lot of slices.
It's not that hard to use a larger number of slices. For instance a network on chip can use up resources quickly.
8400 is only about 20, 400 slice cpu's.

Simply double or quadrupling a datapath width can suddenly use 4x the resources.
Add in barrel shifters, more extended operations (bitfield, SIMD) and the resource usage explodes.

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Wed May 10, 2017 12:23 pm
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Just to note, Rob, the most expensive in-stock FPGA is a bit over $21000. There's plenty of room at the top!


Wed May 10, 2017 12:27 pm
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Quote:
the most expensive in-stock FPGA is a bit over $21000. There's plenty of room at the top!

Yikes, that's a bit over my budget. It does show that tons of LC's are available.
But a decade from now what will the $10 FPGA look like ? What is the trend in price per LC ? I started with a 800 LUT (200 slice) FPGA. (XC4010)
It may not even be possible to get "tiny" FPGAs / PLDs in the future. So why pull one's hair out minimizing a design ?

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Wed May 10, 2017 12:52 pm
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It's a question, but I'm not sure it's a question for this thread. This thread poses an 8-bit CPU challenge, to fit in 128 slices. That's what it is. You should feel free to post up an 8400 slice challenge!


Wed May 10, 2017 2:05 pm
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I'm busy this week, but I'll try to put up a github repository this weekend. I've restored pretty much all that was lost, and slice count has actually gone done a bit due to some different choices, but I want to get to a point where I have a complete subset, and not just a bunch of loose ends. In the process, I've also reduced some instruction cycle counts, even though that's a low priority.

I've noticed the slice count is very volatile, sometimes a small chance can add dozens of slices, and sometimes I can add a bunch of other stuff for very little cost. The tools also leave plenty of slack. For example, mixing adders with other operations or muxes often doesn't work very well. If you make 4 different additions followed by a 4->1 mux, you get a lot more logic than when you mux the inputs first, and feed them into a single adder. Ideally, the tools should be able to rewrite the first into the second.

Also, the encoding of the state machine makes a lot of difference. A few experiments seem to indicate I'm better off with a small state machine, with fewer states, and some extra registers on the side to modify the behavior.

Currently I have: ALU operations on mem/reg, without result going either way, a MOV instruction between mem and reg, and an unconditional branch with 8 bit offset. I'm now working on a PUSH instruction, which is tricky because it writes both register and memory location.


Wed May 10, 2017 6:11 pm
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