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| free verilog simulator (and the learn-by-fixing CPU) http://anycpu.org/forum/viewtopic.php?f=3&t=382 |
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| Author: | BigEd [ Mon May 22, 2017 2:43 pm ] |
| Post subject: | free verilog simulator (and the learn-by-fixing CPU) |
This Hackaday article might be of interest: Simulating the learn-by-fixing CPU (video within) Quote: Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation. I wonder if EDA Playground might not be a good way to share and experiment with (smallish) CPU designs? It seems you can share a URL which drops you right into a particular project, can run a simulation and view waveforms (although possibly with a necessary signup step) Otherwise, for free simulation, there are open source simulators (icarus, cver, verilator, ghdl, myhdl) and free simulators (isim in the Xilinx toolchain for example) Edit: while I'm here, I found a verilog tutorial: https://www.nandland.com/verilog/tutori ... nners.html |
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