The demo I'm presenting here consists of the following:

A simple, reasonably fast 6-stage RISC CPU (around 2500LCs in total), it's retiring 1 instruction per clock cycle unless stalled by an extended instruction (no memory stalls, no interrupts, etc.). This CPU core is designed to be a minion CPU in an SoC controlled by another, more general purpose CPU, but obviously on ICE40 8k we only have space for one CPU anyway.
A monochrome 640x480 VGA
An infrastructure for adding extended instructions to the RISC CPU
An optional UART (not used in the demo)
A small 2-port RAM implemented on ICE40 block RAMs, used for both code and data
A very simple extensible C-like language compiler, with an SSA-based optimisation middle-layer and multiple CPU backends. This language allows to inline Verilog into C the same way as one would inline an assembly.
There is a demo program displaying a monochrome Mandelbrot set (computed in fixed point).