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Linux-capable quad-core RISC-V chip - SiFive's Freedom U500 http://anycpu.org/forum/viewtopic.php?f=3&t=497 |
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Author: | BigEd [ Tue Dec 19, 2017 8:07 pm ] |
Post subject: | Linux-capable quad-core RISC-V chip - SiFive's Freedom U500 |
. From the latest RISC-V workshop proceedings, SiFive described their upcoming SoC (which includes a 'ChipLink' to your FPGA design.) There's a small housekeeping core and four high performance cores, each with L1 cache, and a shared L2. The cores run at 1.5GHz. See the PDF here. What surprised me most was the amount of chip area dedicated to the DDR interface: Attachment: SiFive-Freedom-U500-RISC-V.png [ 712.11 KiB | Viewed 7045 times ] Quoted Performance:
• 2.75 CoreMark/MHz Of course it doesn't have to run Linux, but that you can is an indication of the CPU capabilities. |
Author: | Manzino [ Wed Dec 20, 2017 3:51 pm ] |
Post subject: | Re: Linux-capable quad-core RISC-V chip - SiFive's Freedom U |
Color me impressed. I hope this project becomes a great success. How much is this going to cost? |
Author: | hmn [ Wed Dec 20, 2017 6:17 pm ] |
Post subject: | Re: Linux-capable quad-core RISC-V chip - SiFive's Freedom U |
The video for that presentation: https://www.youtube.com/watch?v=Mp6znwaZ5xo Also, one of my favourites from the same conference so far: The Maxion supercomputer-on-a-chip, presented by industry veteran Dave Ditzel (Sun/SPARC, Transmeta/Crusoe). 4000 RISC-V cores, designed for a 7nm process. https://www.youtube.com/watch?v=f-b4QOzMyfU |
Author: | BigEd [ Wed Dec 20, 2017 8:58 pm ] |
Post subject: | Re: Linux-capable quad-core RISC-V chip - SiFive's Freedom U |
Thanks for the links. A couple of useful summaries of the two days: http://www.lowrisc.org/blog/2017/11/sev ... p-day-one/ http://www.lowrisc.org/blog/2017/11/sev ... p-day-two/ |
Author: | BigEd [ Thu Dec 21, 2017 7:29 pm ] |
Post subject: | Re: Linux-capable quad-core RISC-V chip - SiFive's Freedom U |
. Making this into something of a RISC-V thread... this talk is a good one for seeing the interaction of micro architecture and physical design. Those ten port register files are not going to place and route themselves. BOOM v2: An Open Source Out Of Order RISC V Core [video] |
Author: | robfinch [ Fri Dec 22, 2017 6:34 am ] |
Post subject: | Re: Linux-capable quad-core RISC-V chip - SiFive's Freedom U |
I'm tempted to try and learn CHISEL now. I'm wondering how it would compare to a straight vhdl or Verilog coding. It sounds like it does a lot of the work of connecting things. There seems to be a lot of LOC to BOOM though. 16,000 LOC, I think I'm sitting at < 10,000 Verilog for my own. The LOC has to be manageable for the size of the project. Quote: Those ten port register files are not going to place and route themselves. All the videos look like a move to popularize RiSC-V. The pundit's say RiSC-V, but I prefer my own cores. |
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