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 Memory Nuts 
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Joined: Sat Feb 02, 2013 9:40 am
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Location: Canada
What's got me going now is the fact that I have half a dozen older 1Gb, 2GB memory modules and I can't put them to use. Is there an easy way to interface to the modules so that they can be reused ? As in for a low speed hobby type computer ? (Somewhat of a rhetotical question).

The other thing I tried to find was a PCI-Express bus chip that would convert to a simpler bus. Was thinking about trying to use a new bus standard in a homebrew computer.

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Robert Finch http://www.finitron.ca


Thu Mar 08, 2018 6:27 am
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Joined: Wed Jan 09, 2013 6:54 pm
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What kind of memory modules are those? 72 pin double sided connection - or something even more dense? Are they the little ones for laptops or the big ones for desktop and larger?
https://en.wikipedia.org/wiki/DIMM#Variants

It looks like SIMM capacity only goes up to 128M:
https://en.wikipedia.org/wiki/SIMM#72-pin_SIMMs


Thu Mar 08, 2018 8:38 am
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Joined: Sat Oct 28, 2017 12:16 am
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I think the interfacing with modern DIMMS is quite complex. I remember reading about how the memory controller automatically negotiates latency settings for multi-channel operation depending on which combination of modules are installed in which slots.


Thu Mar 08, 2018 5:49 pm
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I think anything before DDR mightn't be too bad. But you sometimes see DDR on FPGA dev boards - and the FPGA vendors will often supply a library to interface to DDR.


Thu Mar 08, 2018 6:29 pm
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Joined: Wed Apr 24, 2013 9:40 pm
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Location: Huntsville, AL
Rob:

Not going to claim any expertise on this topic, but I've built a couple of projects using the PCIe Endpoint Block logic built into most new Xilinx (and likely, Altera FPGAs). One is a product that my company brand labels for a major industrial automation company. Both projects used LXT parts: one a Virtex 5 and the other a Spartan 6. In both cases, the PCIe interface (8x - Virtex-5, and 1x - Spartan-6), was very simple to implement. Like any high-speed interface, care must be taken in the layout of the multi GHz differentials pairs and of the reference clock, which is typically 100 MHz. Other than that, normal HDL practices were all that we needed to get our 1x PCIe interface converted in the FPGA to essentially connect to an ISA-like bus. The only significant downside, if you choose to use the built-in PCIe end-point blocks in the Xilinx parts is the price. For our application, we also sucked in all of the ROM and RAM used by an external application-specific processor by using level shifters to translate the +3.3V LVT I/O of the FPGA to the old +5V levels of the processor. Cost effectiveness was not a particular consideration, but it certainly puts to bed some of the obsolescence issues we've been having with Flash and SRAMs needed by the processor.

With the Virtex-5 project, I also used two 64-bit DIMMs for mass storage on the card. The Memory Interface Generator (MIG) from Xilinx was fairly easy to use. However, the only problem that I can see you having with it may the use of non-Micron memory. If I recall correctly, all of the supported RAMs and organizations are for Micron devices.

This is like the problem I've had with the in-system Flash writer from Xilinx which only supports a limited number of vendors and parts. They problem was acute enough that we wrote our own loader that worked independently of the installed parts. In other words, as long as the parts were compatible from a JEDEC perspective, our programmer did not care about the various manufacturer's ID data that typically sent the Xilinx programmer off into the weeds.

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Michael A.


Thu Mar 08, 2018 8:12 pm
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I think the ram is ddr2 168 pin simms for a desktop workstation. I found also some older regular PC133 sdram. The sdram looked like it might be not to bad to interface to. It looked possible to initialize the sdram using just software. But I gave up trying to find cad libraries for sockets and such. Anyway I’m going with regular sram (one of Garth’s modules).

I looked at PCI express because it’s a relatively new standard. For my project I don’t need the multi-gigahertz high performance though. I just needed a way to interconnect boards. I figured that PCIe connectors would be inexpensive and guessed there might be a chip around that bridges to one of the older bus standards. Is there a recent standard low speed bus ? (Address + data + control)

The interfaces can be found in FPGA components but then I’d have to solder a BGA probably. I suppose I could use an FPGA with a breakout board. The other issue with FPGA is power consumption. The whole project could probably be done in a single FPGA, but this is somewhat of a retro project. I haven’t worked on a real hardware project for a decade.

So I’ve pretty much decided just to use 50 pin header strips and sockets to connect things. It’s a low speed bus (2 MHz) for hopefully a low power computer.

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Robert Finch http://www.finitron.ca


Fri Mar 09, 2018 5:16 am
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Joined: Wed Apr 24, 2013 9:40 pm
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Rob:

I like the simplicity of SRAM. A simple ribbon-cable based interface is certainly not a bad way to go.

Since you're quite proficient with programmable logic, I might suggest implementing a hybrid bus using a nibble/byte serial bus similar to your NOC concept you've described on this site before. Four or five RS-485 transceivers would easily support differential, bidirectional transfers at 3, 6, or 12 MHz.

Intel does have a document that I've looked at several times over the years that may be appropriate for your project. It's their Low Pin Count (LPC) Interface. I've considered implementing it several times, but in the end I went with the built-in IP blocks (PCIe or 10/100/1000 Ethernet) of the FPGAs I used for the projects.

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Michael A.


Fri Mar 09, 2018 3:39 pm
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