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 a simple cpu 20 bits wide 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Garth wrote:

We've had a discussion or two on the 6502.org forum about project computers you could get running without the help of another computer.

Well I can help, here if you got the parts, like 28C16's.
Code:
Ben's Design of a simple cpu 20 bits wide, with two 8 bytes per word.
Random logic design with TTL or LS TTL. The ALU makes use of the off
state on the 74x170 ram to give 0 on the A alu input.The B input
is active high but the ALU is active low. Only A few data sheets(74F181)
show this mode. Front panel and interupt logic not included.The alu mode
is the a simple decode of the 181 operands, undefined at the moment but
ADD/SUB and logic. Alu operations are ADD,INC A,and alu OPERATION.
28C16's EEPROM are used the top 4k address space to emulate core memory
as a front panel write operation. Regular static memory is used elseware.

Table #1 Instructions
M= MEM B=BYTE J=JUMP S=STORE  !M&B IS SHIFT
[M:B:J:S][ALU][AC:IX][####][####]       : OPCODE
Table #2 state cycle

 A IX+# -> MAR                          / EFA (WRITE BACK CYCLE CORE) FETCH
 B AC   -> OUT  READ/(WRITE ON STORE)   / CORE MEMORY READ OR NEW DATA
                TEST AC ON JMP          / WRITE BACK OR DATA WRITE BACK
                SAVE AC TO A FOR JUMP AND SAVE  / INPUT DATA (BYTE CLEAR 20..9)
       
 C PC+1 -> MAR                          /
   PC=# -> MAR FOR JMP                  / EFA FETCH

 D AC   -> OUT  IF OP AC=AC+OP          / INPUT DATA (CLEAR 20..9)
                ELSE INC
                IF SHIFT AC=AC SHIFT
                IF SET ACC ON CC CY IN is 1

Table #3 C is ac with carry
 REG FILE  IX
 0 C(PC)   PC(PAGE)
 1 A       Z
 2 X       X
 3 S       S
Table #4 is the alu bit slice repeated 5x ic's 1 thru 6
The 74ls298 could be replaced with another 74ls157 and 74ls175 D f/f.


          IC1        IC2        IC3          IC4       IC5

 BUS IN  |INPUT| --@|ALU|  -- |MULX SHIFT|--|2/1  |--@[BUFFER]OUT BUS
 LOAD/CLR|REG  |   +|   |   +-------------- |REG  |+---
                   |                                  |
          IC6      |                                  |
       +-|RAM]---- +    4 BIT ALU SLICE               |
       | |O/C|                                        |
       +----------------------------------------------+
IC1 74LS161 IC2 74LS181 IC3 74LS157 IC4 74LS298 IC5 74LS38 IC6 74LS170
IC31 74LS00

Table 4 is a core style memory with a close idea
of gate delays.

  MEMORY CYCLE CORE STYLE  1.8 US
  300 NS CLOCK .9 US HALF MEMORY CYCLE
  ####________####________  CLOCK A
  ____####________####____  CLOCK B
     <READ>      <WRITE>
  <600 NS OUT><600 NS MAR>
           <IN>

Interupts just clear the PC some how
after clearing the IR register. The idle
state also clears the ir for the front panel.
Adress load,deposit and examine as well as run/stop.

To summerize A Simple design makes use of a wide word length,
indexing and MSI TTL that came out in early 1970's.


Thu Oct 10, 2019 7:48 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Slight error PC + 1 to A for Jump and save


Thu Oct 10, 2019 7:51 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1440
Thanks for describing your CPU design oldben. I'll re-organise your post into a new thread, as that seems most appropriate. This forum is small enough and quiet enough that you can be sure that everyone here will see every post.


Thu Oct 10, 2019 8:21 pm

Joined: Tue Dec 11, 2012 8:03 am
Posts: 282
Location: California
oldben wrote:
Garth wrote:
We've had a discussion or two on the 6502.org forum about project computers you could get running without the help of another computer.

Well I can help, here if you got the parts, like 28C16's.

I should have specified that the discussions were specifically about 6502-based computers. (It was a 6502 forum.) The microprocessors are no harder to get than the EEPROMs, and EEPROMs need a programmer. My first EPROM programmer was totally manual (in 1985) since I did not have a computer to control it, but it was so slow and prone to human error that it was nearly useless. I had not heard of EEPROMs yet, and I was using 2764 EPROMs, and a mistake usually meant erasing the whole thing (rather than just a byte), in UV light, and starting over.

The idea behind the dead-start computers was that you could, with front-panel switches, or something like a 74-family logic-controlled bar-code reader that read bar code written on quadrille paper by hand with a pencil or marker and corrected with an eraser or white-out, load in enough software to get started.

I seem to remember that the ROM of one or more of the early Hewlett-Packard desktop calculators was actually a bazillion diodes on PC boards. I wish I could remember some good search terms to find the page I'm thinking of. The entire huge, heavy calculator, with lots of PC boards, had no ICs!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources


Thu Oct 10, 2019 8:25 pm WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Having just finished a more complex 20 bit cpu, I came up with 45+glue chips for the ALU section
and ~ 30 chips + 2 256 x 8 fuse proms for the control section. In my case 2 CMOS 22V10's.
The simple cpu can be ballparked at 35+glue for the ALU section, and 15 chips to decode states
and 30 chips for the basic functions. In both cases about 80 TTL total.
Time to think about a simpler complex 20 bit cpu,Well back to the drawing board ...


Sun Oct 20, 2019 7:12 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1440
Is that a paper design that you finished, oldben, or something you built and were able to run code on? Or somewhere in between?


Sun Oct 20, 2019 8:30 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
I am useing Altera DE1 FPGA to protype my designs.I have a working 18 bit design using TTL macros for the TTL logic like a 74181. The FPGA software does have few quirks, giving me random timeming glitchs depending on the phase on the moon, keeping me from bigger ideas.My 18 bit software still needs to written,and debugged.The 18 bit design has better front panel display to I can have the blinking lights display.It however is too complex for the 20 bit cpu, that problem needs to addressed.


Sun Oct 20, 2019 10:17 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
I have expanded my complex 18 bit cpu to 20 bits, for the simple reason the simple 20 bit cpu
has a very primitive subroutine call that is a real pain to as the return address is saved in the AC.
The complex cpu, saves the PC on bottom of the stack, permiting limited argument passing in
the AC and IX registers.
Using LS TTL logic I have a total of 24 SSI/MSI LS chips and 3 Proms emulated on the FPGA card.
1KB of rom is used for a simple bios. A SD card will be used to emulate 2 8" floppies or 2 reels
of DEC tape with 10 bits per byte and about 240Kb per media. Simple console I/O is working but I need to write and test disk software. 32Kb is planned base memory with 10Kb for a primitive O/S, with no interupts.
A TTL version would have 5 small proms and 2 more glue chips giving a total of 30 chips.


Sat Nov 16, 2019 7:30 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1440
Are you hand-assembling for your BIOS, oldben, or have you written an assembler?


Sat Nov 16, 2019 8:46 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
I have a cross assembler written in C and simple microcode assembler written in C.
Both are quite hacked to death. I also am writing a simple high level langage in C
for software development, since I could find nothing simple to port to my machine
that was stack based code (Tiny C) or 386 output (real C).


Sat Nov 16, 2019 7:27 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1440
Sounds pretty good. Do you plan to share your code?


Sat Nov 16, 2019 8:02 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
It is too buggy at the moment, to release anything. If any one has a ALTERA DE1 fpga development kit
I can share the bit stream data. The hardest part of code writing is the DOCs.


Sat Nov 16, 2019 8:23 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
* Stomp Stomp Stomp * More bugs killed. A Basic Cpu redesign would use 3 32x8 proms
and run about .68 us with TTL for 18 bits with a 72 pin bus with core stye memory.
A deluxe 18 bit version in LS would the be same clock but a Dram memory cycle. Ten more chips in the data path. The control path would use larger proms 2 256x8 , 1 32x8 but only a few more glue chips. At the moment I drawing schematics from the FPGA for the TTL version, and will get the final sizes and better ideal of timing over the week end.


Fri Jan 03, 2020 10:17 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
I have decided just to stick with 18 bits rather than 20. Rough notes have about 27 chips for control
and 50 chips for the alu. 4.9 mhz with a 4 phase clock, similar to the 6809. 3 proms used and 72 pin connector. A 88 pin connector is needed for 20 bits.
Once I get the proms entered into kicad, I can then work on the schematics.


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Wed Feb 19, 2020 5:36 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
I have a draft version of the schematic of the control section for the 18 bit cpu. Some cleanup still required, moving labels and logic checking. 20 bits would be similar with a bigger bus connector and
minor opcode layout changes. Sill have no idea about the size of the PCB. 3 main PCB's - control - alu -display/front panel with memory/io cards as needed. <cards1-5><display><alu><control>


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Sat Feb 22, 2020 5:49 am
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