.
Found this interesting presentation (20 page PDF)
ARM810: Dancing to the Beat of a Different Drum by Guy Larri
(Mentioned on Who are the Computer Architects? by Mark Smotherman)

with this pair of pipeline diagrams:


The ARM7's 3 stage pipeline is extended to 5 stages, there's a double-pumped read port to the cache, and the clocks-per-instruction improves from 1.9 to 1.4

Just came across wikichip's description of ARM2:
https://en.wikichip.org/wiki/acorn/micr ... rm2#Core_2

Maybe some day, I will convert my CPU74 to Von Neumann, and implement it using the original 3-stage pipeline of the ARM1 and ARM2. I believe the architecture is totally suitable for that.