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"FPGA Softcore SoC shootout" - six cores compared http://anycpu.org/forum/viewtopic.php?f=3&t=750 |
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Author: | BigEd [ Mon Jun 22, 2020 6:05 pm ] |
Post subject: | "FPGA Softcore SoC shootout" - six cores compared |
. An interesting blog post: FPGA Softcore SoC shootout 6 cores, 5 architectures, including POWER, SPARC and RISC-V. One very small, some very fast. Quote: The ZPU is tiny. really tiny. A small SoC with a uart is 469 LUTs and 287 FFs The CPU alone uses 369 LUTs and 189 FFs. Quote: Some things stand out. 4 cores are 1000 LUTs or smaller and the other 2 are a lot bigger. This most likely is due to build in multiplier/divider blocks, which can be disabled on a CPU like Vexriscv. With 6 CPU’s tested I have tried 5 different CPU architectures. Only RISCV was in 2 CPU’s, but there are a lot of other RISC-V CPU projects. All in all, this was a fun project to do, and took quite some evenings in total. There are a lot of other CPU’s and I cannot test them all. And frankly, I have seen enough CPU’s for now |
Author: | robinsonb5 [ Mon Jun 22, 2020 6:47 pm ] |
Post subject: | Re: "FPGA Softcore SoC shootout" - six cores compared |
Nice to see ZPUFlex getting a mention there - that was one of my previous pet projects! |
Author: | oldben [ Mon Jun 22, 2020 10:47 pm ] |
Post subject: | Re: "FPGA Softcore SoC shootout" - six cores compared |
I say this more like comparing apples to oranges. Important details are masked out by the WOW speed factor of the VHDL compiler used amd the best FPGA. I think the first version of Micro Baze was hand compiled for speed. Using 16 bit x 1 Xilinx block rams as a 16 x n register file and tristate logic for the ALU. This was 20 years ago, and the link has vanished off the web. Compare say clock cycles for instructions, and I bet most Risc's run at the same speed. Ben. PS: Found the site. You have to dig a bit for the first cpu version. http://fpgacpu.org/index.html Let us see today vs 20 years ago. |
Author: | robinsonb5 [ Tue Jun 23, 2020 8:06 am ] |
Post subject: | Re: "FPGA Softcore SoC shootout" - six cores compared |
oldben wrote: I say this more like comparing apples to oranges. Important details are masked out by the WOW speed factor of the VHDL compiler used amd the best FPGA. I think you might be looking at it from a different angle from the author - I think the intention here is "So you're working on an FPGA project and you need to embed a CPU to handle housekeeping tasks. Here are some options, with the pros and cons of each." Quote: Compare say clock cycles for instructions, and I bet most Risc's run at the same speed. Well he does quote DMIPS/MHz, and yes most RISC designs will have pretty similar performance - certainly within an order of magnitude - so other factors (such as footprint and how painful the CPU is to integrate or debug) will be a tiebreaker when deciding which to use. Quote: PS: Found the site. You have to dig a bit for the first cpu version. http://fpgacpu.org/index.html Let us see today vs 20 years ago. Looks like some good reading material there - thanks for the link. |
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