emulsiV is a visual simulator for Virgule, a minimal CPU core implementation based on the RISC-V architecture. This simulator is intended to be used as a tool for teaching the basics of computer architecture.

The user interface shows the structure of the datapath and animates the data transfers between functional units. The execution of a single instruction is decomposed into several steps (fetch, decode, ALU, mem/reg, PC) for educational reasons, but the intent is not to reflect a specific sequencer or pipeline implementation. In fact, we don't plan to simulate a pipeline in more detail.