CPU's for Bootstrapping: The Simple, The Verified, and The Necessarily Complex
NAND2Tetris by Nisan and Schocken (Guide that teaches hardware step-by-step in fun way with simple CPU emerging)
J1 by by Bowman (16-bit Forth CPU in 200 lines of Verilog that does 100MIPS on FPGA's)
H2 by Howe (Modified, VHDL version of J1 with detailed description and Howe's code MIT-licensed)
RISC-0 by Wirth (Simple, RISC CPU & SOC designed for Oberon language with detailed docs and source online)
JOP by Shoeberl et al (Embedded Java processor that takes up 1830 slices on FPGA)
Scheme Machine by Burger (Scheme interpreter implemented as CPU using formal methods)
ZPU by Zylin AS (Tiny, 32-bit CPU for deep embedded apps in 440 LUT's)
J2 by Landley et al (Clone of cost-efficient, SuperH-2 CPU in open-source)
VAMP by Beyer et al (Formally-verified, DLX-style processor in 18,000 slices on Xilinx)
Leon3 by Gaisler (Industry-grade, 32-bit SPARC w/ auto-configuration of core and GPL license)
Rocket by Univ of CA (1.4GHz RISC-V CPU and generator for customization)
OpenPITON by Princeton (25-core, shared-memory, SPARC CPU open-sourced and very scalable)