Every body and their dog, seem to having a new RISC design.
At one time MIPS was king of the heap, now it is some kind ARM.
I liked the AMD 29000, but that is long gone.
Why do we need a new design? Why is RISC More Complex now
than the CISC's it was ment to replace? Did they all die as Apple and
Pc clones fought over the chip to use in the next computer?

Ben.

No, but I tend think of it in terms similar to those expressed by Rob Finch on another thread.In the case of AMD, the 29k family just did not do as well commercially as the their x86 architecture. To keep 29k's performance in step with the performance improvements made in the x86 architecture, additional technical resources were needed and the ROI just wasn't there. I think the same same can be said for the MIPS and SPARC architectures, although MIPS continues commercially in some Microchip products. ARM's volume provided the company the necessary resources to keep improving the architecture on the performance front.

A GHz-class processor requires much more complexity to perform adequately, and that complexity requires significant technical resources to achieve. In the case of ARM, some of the technical improvements in the architecture are driven by the licensing model that ARM employs. IOW, Apple (and other licensees) provide some of the technology that drives the improvements in the processor architecture. The large volumes that ARM has in the various markets it services provides the resources that are needed to maintain the architecture and drive improved performance.

I use ARMs, PICs, and other processors in some of the products that we design. We are increasingly using ARM-based microcomputers / microcontrollers in our newer products because the licensees add peripheral functions to the base architecture that are better matched to the industries we support. ARM itself is not doing that work, it is the licensees themselves that are developing and improving their own chips based on the core ARM licensed to them. I don't typically use GHz-class ARM processors, but a 60-120 MHz ARM core executes the algorithms that we originally ran on 8051 and 68HC11 microcomputers much faster.

The point is that with the exception of ARM, the other main RISC processor architectures were sourced by a single shop, and they were focused on competing primarily with x86-based computers. When their offerings could not increase market share, they didn't shift their IP model. ARM shifted to their IP model decades ago, and they are now penetrating the market that would have been occupied by x86 if that architecture had been able to lower their power utilization requirements.

I used to be adamantly opposed to anything x86, but now I will use either x86 or ARM, and the decision is based primarily on power / thermal management and security issues, or whether the application must run on Windows, Linux, or both. The other architectures, including PowerPC, just have not achieved the same performance levels as provided by x86 or ARM, and that is primarily driven by the lack of resources, which in turn, is driven by a lack of market.

I kind of thought that. The X86 is the king of the hill for many factors, not just computing
design.

I say It is all Just agressive marketing, for being faster. All the major tricks have been found
years ago. Now it seems to be juggling thngs around for speed at the cost other operations.
That GHZ X86 is still slow with all the complex crap added by OS marketing. A file picker menu
under windows needs 5 seconds to refresh a small directory (downloads), and pop up a window giving useles
file information. I wonder how fast that directory would refresh as a 'cloud object'.
Ben.

How about RISC-V? - a clear descendant of MIPS, clean and simple design (It takes two evenings to get it implemented from scratch in a logic circuit simulator), increasingly popular, with new microcontrollers (starting with GD32VF103 back in 2019) and SBCs similar to raspberry Pi emerging every month. Looks like a solid platform with some future.

Are there any real new RISC designs?

(Not counting the hobby level things here and elsewhere).

The newest, I think is RISC-V and that can trace its roots right back to the very early days of Berkeley RISC in the early 80's.

From what I gather, the RISC-V community felt the needed a new design not for "bigger, better, faster", but to free-up the "shackles" of the commercially licensed ARM designs. It's starting to gain traction although will it ever catch up in performance terms with ARM? 30 years of investment and $billions suggests not in the near term, but there are many who'll use it anyway just because they can.

I have started to look at it myself - and I like what I see - it's "clean", I wrote an emulator for it in a few short while and then re-wrote my bytecode interpreter in RISC-V assembler which was a joy compared to the previous CPU (65c816). It's been a very very long time since I looked at ARM assembler.

Are they more complex than CISC? Looking at the current x86 stuff then no - not by a long shot! Compared to the CPUs of the 90's then.. Maybe, but we have come a long way since then. I also fear you're confusing applications software (e.g. your file picker) with native CPU 'grunt'. See that rounded and shaded corner on your 4K screen? Well, there's another million lines of code that pulled in 3 'frameworks' just for that - I blame lazy programmers, not the chip architecture, but I think it's always going to be a race for the chip architects to try to keep up with what the lazy software weenies want/demand, no matter what the underlying CPU is...

-Gordon

My understanding is that RISC-V is an ISA designed with the intention that no-holds-barred high performance implementations will be straightforward. In other words an ISA without awkward aspects which complicate a high performance design.

They also define it as a series of optional extensions to a core ISA, which might be intended to help out the small low-power implementations at the other end of the cost curve.

As it happens, they also went for an open architecture without licensing obstacles. Although it sounds like it will take work to keep some sort of core compatibility between the many implementations and extensions - that is to say, to avoid too much fragmentation.

I get the impression that a lowest-cost serial implementation is very small indeed. In fact I think it's only a few pages of code too, if I'm not wrong - instruction decode is (intentionally) not a great challenge.

Not just ARM, but even more so MIPS - which had a short-lived dalliance with being slightly more open when RISC-V appeared, but wasn't nearly open enough to threaten RISC-V's adoption (and don't you *dare* think about adding custom instructions!).



Almost certainly not - but it probably doesn't need to - not everything needs the grunt of Apple M1 silicon, and RISC-V will be a good fit for routers and suchlike - the kind of thing where MIPS hasn't yet been entirely supplanted by ARM. The next generation of the ESP32 moving from Xtensa to RISC-V is an indicator of what to expect, I think.



Ah, good old "ransom note programming." At least kidnappers are traditionally savvy enough to include just the bits they intend to use...



Sadly so. I first encountered Sage Instant Accounts on a 486 PC with 4 meg of RAM. I'm currently using the closest thing that still exists, on a Core i5 machine with 4 gig of RAM and an SSD. The machine's three orders of magnitude faster, yet the software feels no more responsive - sometimes even slower. Something has gone horribly wrong for that to be the case.