My ALU has CBEQ that may act as -1,0,+1. And bipolar A-B,B-A subtraction as well. I had thought of forcing B to 02h.
viewtopic.php?f=23&t=955#p7773CBEQ and B together might allow INC/DEC : -3,-2,-1,+1,+2,+3. But the zero option becomes an unreachable target.
If B were forced to 01h or FFh instead (as you suggest), -2,-1,0,+1,+2 become the reachable targets.
Forcing B to Zero may have other, better uses, like an add with conditional B=0 might help when multiplying.
But there seems little point wiring for any of these complications, I suggest lookup instead.
Suppose A and B register banks might be mirror written 32Kx8 MRAM or NVSRAM, but act as independent channels when read.
Now, there is no obligation to use all of those registers. Might make for crazy long instructions, but also no rule against it.
Suppose the first 256 registers hold all constants 0-255. Support for an immediate mode becomes no longer necessary.
Everything could be indirect, pseudoimmediates by way of constants. If the next 256 act like normal GP registers, the bit
that differentiates between bank 0 vs 1 works exactly like an indirection bit. Except a tabled behavior instead of wired.
Or maybe the next few banks barrel shift? Convert to/from BCD or Grey. An opportunity for arbitrary input filter abuse!
As you go wider than 8, the constants require ever larger tables in register memory, quickly becoming unreasonable.
Aforementioned mirror writes might be worthwhile to option as A, B, both, or neither.
Default mirror writes waste half of register memory. Some mirror writes may never be read on the alternate channel.
Specifying the write target(s) adds one or two bits to every instruction, which may already be far wider than the data.
You may need no other memory but 32K+32K registers. As with B=-1 or B=02h, these half-baked ideas might strike
gold, or open a spring-loaded can of multi-tentacled wriggling madness. Explore!