Are there any RISC(well, include others too if applicable) architectures where the r0 register is not always 0?

As RISC is typically "source_A OP source_B -> destination_C" I was pondering if it would be possible/beneficial to have r0 not be 0 when used for source_B? Are there any opcodes that wants to use r0 as 0 but needs to have it in the source_B position?
My(well, someone probably have thought of this long ago) idea was to interpret r0 as -1 when used in the source_B position.

This should give you some "free" instructions by just shuffling around the first and second register used (68K order):
- plus 1 (sub rX,r0,rD)
- minus 1 (add rX,r0,rD)
- not (eor rX,r0,rD)

etc, or are these covered with immediate value versions of the opcodes?

If I was doing a 32 bit RISC I would have 6 instruction types
A) reg op
B) load/store
C) jump on condition/jsv
D) shift
E) half word #
F) ireq service
Reg 0,#0 reg 1,#1 reg 2,#2 reg 3 flags,reg 4# 4

They are covered by immediate instructions.

PowerPC. r0 may be used as a general purpose register except for a couple of special cases like ADDI and Ra of memory ops where the register specified as r0 returns a value of zero.
It saves a little bit of logic in the bypass multiplexor to treat r0 the same as other registers. But there is extra logic in the decode stage required to force source_A to zero for certain instructions.

In one design I had r31 reading either the stack pointer or the instruction pointer depending on the instruction and operand position. Making the instruction pointer readable and sometimes even writable is also present in some designs.

ARM. r0 is a general purpose register.

PDP11 (maybe not applicable here), r0 is also general purpose.

-Gordon

In my unfinished 65m32a design, r0 is named z, and it can be used and modified as a source, destination, and address register that can even be auto-incremented and decremented. It is reset to 0 between every executed instruction, but can be used to synthesize several different types of instructions, including "tst", "clr", and even "set" when used with pre-decrement. It is also instrumental in forming "absolute" addresses and "unadorned" literals.

what is a "unadorned" literal?.
In my latest creation,insert evil laugh, I have two 0 registers. One is called Z and will be used
later as base page for relocatable segments. The other one called I and is used for I/O and operating
system stuff. My bigest problem is how Retro to make the design. 40 years ago is 1982, and the PeeSee
era has started. 45 years ago is 1977 and looking at old Bytes, real hardware could not be found for love or
money (Dog slow 16K dram, 3 phase Fixed Disks,Non Stocked 2901 bit slice and Proms, 110 baud typewriters
and 30 cps paper tape,7 track mag tape). Ben.

I have "one" operand, like a 65xx or 68xx. But there's always a register in the operand, even if the assembly language doesn't show it. E.G. lda #LIT and stx ADDR both have a silent ",z" at the end in the strict translation. The reason I put quotes around "one" is because there is an exception for some of the read-modify-write and looping operations. I need to get my rear in gear and dust off the design this summer.

My ALU has CBEQ that may act as -1,0,+1. And bipolar A-B,B-A subtraction as well. I had thought of forcing B to 02h.
viewtopic.php?f=23&t=955#p7773
CBEQ and B together might allow INC/DEC : -3,-2,-1,+1,+2,+3. But the zero option becomes an unreachable target.
If B were forced to 01h or FFh instead (as you suggest), -2,-1,0,+1,+2 become the reachable targets.
Forcing B to Zero may have other, better uses, like an add with conditional B=0 might help when multiplying.
But there seems little point wiring for any of these complications, I suggest lookup instead.

Suppose A and B register banks might be mirror written 32Kx8 MRAM or NVSRAM, but act as independent channels when read.
Now, there is no obligation to use all of those registers. Might make for crazy long instructions, but also no rule against it.
Suppose the first 256 registers hold all constants 0-255. Support for an immediate mode becomes no longer necessary.

Everything could be indirect, pseudoimmediates by way of constants. If the next 256 act like normal GP registers, the bit
that differentiates between bank 0 vs 1 works exactly like an indirection bit. Except a tabled behavior instead of wired.
Or maybe the next few banks barrel shift? Convert to/from BCD or Grey. An opportunity for arbitrary input filter abuse!
As you go wider than 8, the constants require ever larger tables in register memory, quickly becoming unreasonable.

Aforementioned mirror writes might be worthwhile to option as A, B, both, or neither.
Default mirror writes waste half of register memory. Some mirror writes may never be read on the alternate channel.
Specifying the write target(s) adds one or two bits to every instruction, which may already be far wider than the data.
You may need no other memory but 32K+32K registers. As with B=-1 or B=02h, these half-baked ideas might strike
gold, or open a spring-loaded can of multi-tentacled wriggling madness. Explore!

A RISC machine is based on mostly rhe register file architecure. A MOS or FPGA RISC can have more little tricks
than one built with a TTL register file. It boils down to hardware.
Only 0 and 1 needed to be constants on the orginal computers, with a single word size. 0,1,10 might be needed on decimal
machine. With byte adressable memory you now need constants in the range, 0,1,2.4,8 and ADD and SUB and LOAD alu ops.
Oh wait all RISC machines are LOAD/STORE architecure because they don't have ample bits in the opcode to define a full ALU.
ADD,SUB,AND,XOR is it.
Makes bytes now 9 bits wide, ta-da 36 bits, for opcodes.
Now your RISC is back to being a real computer