The core has a separate dedicated instruction pointer. It's RISCV compatible. The least significant bit of the pointer is always zero since RISCV minimum alignment is 16-bits for instructions.
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It would be a better deal, if one could use UNIX pipes. Config | core | verlog | fpga | netlists | hardware GUI is nice but does not make porting easy. What do click on after 5 years, later for a bug
fix, it needs 1 new standard I/O ports. Ben.
I'm not quite sure about this, but I've been pondering if it would be better just to code by hand or use a core generator, which is why I've been working on it slowly. I'm not sure it's the best approach. As it is if something changes down the road, the tool becomes outdated. But many tools are time limited.