AnyCPU
http://anycpu.org/forum/

Core Generators
http://anycpu.org/forum/viewtopic.php?f=8&t=773
Page 1 of 1

Author:  robfinch [ Fri Aug 28, 2020 3:21 am ]
Post subject:  Core Generators

FriscCoreGen is a software program that generates a RISCV compatible core from a template and user selections made in a GUI. Most of the options don’t work at the moment, but I improve it from time to time.

The latest thing included is non-standard immediates (nsi option) where if the immediate value in the instruction is $800 (immediates are 12-bits max) then the next 32-bit word in the instruction stream is used as the immediate value. This works for immediate mode instructions and load / store / branch displacements. It's non-standard as it's not the usual way a RISCV processor works.
Attachment:
FCG.png
FCG.png [ 35.03 KiB | Viewed 2109 times ]

Author:  oldben [ Sat Aug 29, 2020 1:08 am ]
Post subject:  Re: Core Generators

It would be a better deal, if one could use UNIX pipes. Config | core | verlog | fpga | netlists | hardware GUI is nice but does not make porting easy. What do click on after 5 years, later for a bug
fix, it needs 1 new standard I/O ports. Ben.

Author:  barrym95838 [ Sat Aug 29, 2020 3:26 pm ]
Post subject:  Re: Core Generators

Is this method using the instruction pointer as "just another" auto-incrementing address register? That strategy has a lot of history, and I allow the same in my designs ... but I've heard that it can hinder performance, which may be a determining factor in some cases (not mine).

Author:  robfinch [ Sat Aug 29, 2020 6:25 pm ]
Post subject:  Re: Core Generators

The core has a separate dedicated instruction pointer. It's RISCV compatible. The least significant bit of the pointer is always zero since RISCV minimum alignment is 16-bits for instructions.
Quote:
It would be a better deal, if one could use UNIX pipes. Config | core | verlog | fpga | netlists | hardware GUI is nice but does not make porting easy. What do click on after 5 years, later for a bug
fix, it needs 1 new standard I/O ports. Ben.

I'm not quite sure about this, but I've been pondering if it would be better just to code by hand or use a core generator, which is why I've been working on it slowly. I'm not sure it's the best approach. As it is if something changes down the road, the tool becomes outdated. But many tools are time limited.

Page 1 of 1 All times are UTC
Powered by phpBB® Forum Software © phpBB Group
http://www.phpbb.com/