Does anyone know or have the schematic for OSI Model 300 micro? I sort of searcahed ..found manuals and info but no circuit diagram.. interested in being able to mimic it..

It'll be worth posting this question to the 6502 forums on 6502.org

Please share URLs to what you did find, to avoid duplicated effort. I found
http://www.earlycomputers.com/cgi-bin/i ... i?20040601
http://www.osiweb.org/manuals/OSI_300.pdf
http://www.vintagecomputer.net/vcf5/

It's a very low-density PCB, the three large photos at that last link might be enough to trace it
http://www.vintagecomputer.net/vcf5/OSI_300-a.JPG
http://www.vintagecomputer.net/vcf5/OSI_300-b.JPG
http://www.vintagecomputer.net/vcf5/OSI ... -angle.JPG

pretty much same results ... thought it be easier to figure how it actually worked with the circuit ..Strange that it did not have one..

mike

Hi chessdoger,

If you're still looking, I just came across ChristopherB's May 5th blog entry about reverse engineering and building an OSI 300.

Gee, that's a clever design!

Cheerful regards, Mike

That is excellent!! ..I'll see if I can export to to Diptrace and maybe do a pcb for it

Brilliant! I think a little study might be rewarding... switching the power supply to tristate the buffers is a new trick to me!

The buffers are actually open-collector, not tristate. The internal circuitry of a 7417 section (below) clarifies how the Model 300 can get away with switching off the 7417's power supply -- but it's still a clever trick!
Yes indeed -- I agree!

-- Jeff

Being "hardware challenged", may I ask a question, please, guys?

Shouldn't there be pull-ups on the D7 through D0 data lines for the data input switches to work correctly, or, is there something in the 7417 input circuitry that's providing a sort of pull-up?

TIA... Mike

Yes. In fact, as a general rule the inputs of all TTL family (74xx, 74LSxx etc) logic gates inherently "want" to pull up. If left unconnected they will assume the high or "1" state. (This is not the case with CMOS families such as 74HCxx, 74HCTxx etc. Leaving these inputs unconnected is a recipe for trouble.)

As for the OSi Model 300 Schematic, the way it's drawn is less than ideal. I've been eyeballing it very closely, yet am not at all sure I could build a working version. If anyone ( chessdoger ?) wants discuss the ambiguities and iron them out, drop me a PM.

There's at least one apparent error. It seems the NMI switch ought to have pins 1 & 2 connected (as do many of the other switches) but this detail has gotten omitted or obscured.

-- Jeff

Thank you for the info', Jeff.

The most interesting aspect of this circuit (to me) is that it doesn't require any programmed parts (a ROM, a microcontroller, etc.). If you could figure out a way to program an EEPROM with it (after adding decoder and read/write logic), you might have the beginnings of that "starter system" we talk about over at 6502.org that doesn't require a programmed part to get started.

On the other hand, you could do so much more, using fewer ICs, by taking advantage of a programmed part (ROM or microcontroller). For example, you could provide the same 128 bytes RAM and support a similar user interface using a 6502 + 6532 + ROM + decoder logic. BTW, the 6532 RIOT is an interesting device as we've seen it used over the years in several minimal (128 byte RAM) designs such as the Beta, the Cepac-65, the EMUF 6504, and Mike Naberezny's 6504 SBC design (at 6502.org).

I don't intend to build this circuit but I'd love to hear about the ambiguities you mentioned, if you have time. I did spot the problem with the NMI pull-up resistor.

Take care. Have fun.

Cheerful regards, Mike

I apologize; it would've more accurate for me to say I haven't yet reached a point where I clearly understand all the features -- in particular, the various combinations of the mode switches (LOAD, RUN etc). I'm not aware of any specific problem. But I am itching to redraw the schematic. This one somehow fails to communicate function as effectively as others I've seen. Could just be me. Preferences vary, I suppose.

-- Jeff

You might find that the OSI-400 series boards are more useful. The manual includes a schematic for an optional front panel addition which uses similar techniques to the OSI-300. The breadboard version and prototype I designed uses a 6264 in place of the 6810. It could easily be replaced with an EEPROM or NVRAM part with the same or similar pinouts.


The schematic above matches that on the original OSI-300 trainer, with one exception. There was a small mixup with the resistor in the RC circuit that forms the clock. The resistor should be between pin 3 and pin 37. I found this when I assembled the prototype I had made.

I will say that I wouldn't normally have designed the circuit the way that it was done then. In particular non-shorting (break before make) switches are really important when switching between power and ground such as with RUN and RST switches. A pull up or down resistor would probably be a better design. The schematic is drawn with the parts positioned the same as on the original to make it easier to follow along with the board.


The RUN switch controls several parts of the circuit. When connected to Vcc, the processor will access the RAM, and the 7417 address buffers are enabled. When RUN is connected to ground, it will stop the processor from accessing memory, and isolate it from the buffered address lines by turning off the 7417 address buffers. This is important because the NMOS version won't tristate the address lines.

Additionally, RUN connects ground to the LOAD switch and each of the address bus switches, which are normally pulled high by the current limiting resistors. Each of the data switches is also connected to the run output through a small 100ohm resistor. Thus, when they are switched down (on) they connect the corresponding address or data line to form a low on the corresponding input.

When the LOAD switch is activated, the ground connection from the RUN switch is connected through a diode-or to the /W input on the RAM. This completes the necessary inputs to write the data to the RAM. When LOAD is released, the resistor in the diode-or pulls the RAM R/W pin up, and the RAM outputs the current value. This value is output by the data 7417 buffers to the corresponding data LED.

(Thanks for dropping by, and welcome! Thanks also for the writeup.)

Me too... Welcome, Christopher. Thank you again for the time and energy you've spent researching the OSI-300 and for sharing your results.

Cheerful regards, Mike

I see Christopher has posted an update: a nice looking PCB remake:
http://randomvariations.com/2015/06/22/ ... -300-mini/