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 Bitslice CPUs - machines built with the AMD2901 ALU chip 
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There's a good site about Orion, the Unix machine from High Level Hardware in 1984, built using AMD2901 bitslice ALUs, including the product brochure and the microarchitecture reference manual.

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But I thought maybe we could be more general than that, and discuss any interesting machines made using the nibble-wide chips from AMD.
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Of course, Wikipedia has a list of machines.


Wed Oct 19, 2016 2:58 pm
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The Norsk Data ND-100 16-bit minicomputer (designed around 1978) used four AM2901 bit-slice processors in its ALU.


Wed Oct 19, 2016 3:36 pm
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The Norsk Data computer Tor mentions above was a pretty advanced machine. From the data on the machines that I've read, I would have liked working with one. In some regards, I think that the features they incorporated were better than some of the features represented in the PDP11 processors, which given my personal experience were the best processors that I worked with in the 80s.

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Wed Oct 19, 2016 10:23 pm
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I don't know the PDP-11 that well, as I have never used one (except unknowlingly through some VAX console, possibly - it was used as console processor in some VAX machines). But from what I can tell the ND-100 machines were in another division than the PDP-11. The older NORD-10 (from 1973) had 16 hardware interrupt levels (as the -100. The PDP-11 had four), actually 16 parallel register sets too, to serve the interrupts, and was widely used in real-time applications, e.g. as the backbone of the first F-16 simulator at that time. The -10 didn't use bitslice processors afair, but I should re-check - in any case, the ND-100 maintained 100% software (including binary) backwards (and sometimes forwards, if you wrote your software carefully) compatibility with the NORD-10, despite the different technology. They actually managed to keep compatibility all the way from the NORD-1 from 1968 through the final ND-120 from 1985, even though the -1 used a different operating system. Or systems. The bitslice processors disappeared already from the next-gen ND-110 though. (On a side note - I've finally got myself an ND-110 machine recently, after being without ND equipment for more than two decades).

But as this is about the bitslice processors, I'll see if I can dig up some details about how they were used in the ND-100, if there's anything more that can be said about it other than "it used the AM2901".. there are schematics around, but I haven't seen any textual description about it. In any case, the ND-100 wasn't listed in the Wikipedia page mentioned above.


Thu Oct 20, 2016 12:31 am
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I downloaded all of the bitsavers.org data on the Norsk Data ND-100. It's well worth the read.

On the bit-slice processor design front. A lot of 70s and 80s machines used the AMD products. In addition to Norsk Data, DEC, especially for the Floating Point Accelerator Cards/Adapter, the Data General Nova and Eclipse computers, the Analogic AP400 Array processor were all built with the AMD bit slice components.

I came close several times of using this product line. I highly recommend Mick and Brick's Bit-Slice Microprocessor Design for anyone interested in the AMD products and how they can be used. Michel A. Lynch also has a good book, Microprogrammed State Machine Design, on using these types of devices, particularly the last few generations of the AMD and TI bit-slice components, in a microprogramming environment to produce complex state machines he describes as algorithmic state machines.

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Thu Oct 20, 2016 1:57 am
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I was about to express my surprise that a chip from 1975 was designed into machines as late as 1984, but I see on the Wikipedia page that a Russian version of the chip is still in production as of May 2016.

I'll note another bitslice CPU, National's IMP-16 family from 1973 [Wikipedia article] and the corresponding single board computer. (I just came across it in the form of the "M16" computer, as a $150 trade-in option for MITS' Altair machine in 1975.) I note the clock needs a 17 Volt swing!

Edit: more readings here: http://www.cpushack.com/tag/bit-slice/


Thu Oct 20, 2016 9:43 am
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I have been looking through the Orion documentation. A very impressive machine, from the specifications. If I had been exposed to a Unix machine like that in the mid-eighties it would maybe have been difficult to go back to something else, like VAX/VMS. And yet, I never ran into the Orion back then - this is the first time I've heard about it.
It's a bit surprising though that they could get that good performance out of the AM2901 as late as 1984. As I mentioned above, ND used a bitslice implementation of their ND-100 in 1978, but only four years later (1982) they replaced the AM2901-based ALU with a VLSI (Very Large Scale Integration) gate array, in their ND-110.


Thu Oct 20, 2016 1:43 pm
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I came across a number of CYC79101 (the -30PC variant, 30ns) chips, DIP64, a 16-bit bit-slice processor from Cypress. The datasheet says 'Replaces four 2901s with carry lookahead logic'.
It would be fun to try something with these. I have six of them, and three IDT (Integrated Device Technology) 39C10CP, which appears to be a "12-bit CMOS Microprogram Sequencer" (DIP40). The 39C10's are pin-compatible AM2910 / AM2910A replacements. On the board where they currently sit (in sockets), there is one sequencer with two bit slice processors. With RAM (for a microprogram) you would have a little processor, something like this from the Cypress datasheet:


Attachments:
File comment: Cypress CYC901 16-bit slice processor datasheet
CY7C9_datasheet.pdf [550.54 KiB]
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cy7c9101-application.png
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Tue Jan 24, 2017 1:34 pm
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Good idea! Do you fancy a 16-bit machine, or cascading the ALUs to make a wider one?

Any preferred 16-bit architecture? Any preferred way to implement the registers?


Tue Jan 24, 2017 1:48 pm
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I don't know enough to decide yet. I don't have any direct experience with bit slice implementations, I have as I mentioned used computers where the ALU was implemented with a number of 2901 processors, but I did not study the layout in detail.
The board which I have here comes from a prototype of a supercomputer from back then. This particular board combines two and two CY7C901 with one sequencer, in three groups, with various glue logic, RAM, and programmed logic. If this is used as 3x32-bit ALUs or something else I'm not sure. There is another board with the actual supercomputing hardware, 128 custom processors. It all cost a fortune originally - I remember the presentation. I'm not grabbing the custom processor board, there's nothing I can use from it. It's incredibly heavy though, with all those processors.. 64 on each side of the board.


Tue Jan 24, 2017 2:03 pm
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Wow, is that the kind of thing to be preserved in a museum? I'd love to see photos.

Possibly 2 of the 3 wide ALUS would be for indexing calculations?


Tue Jan 24, 2017 2:08 pm
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I was just now talking with the guy who kept these boards, but he doesn't have the schematics anymore - he sent it back to a company involved in the original design. They may have wanted it for an internal museum project.
I can take pictures of the boards. I have to hurry though because what I don't take will be scrapped, it takes too much space.


Tue Jan 24, 2017 2:18 pm
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BigEd wrote:
Possibly 2 of the 3 wide ALUS would be for indexing calculations?
I was thinking that, too.

Tor wrote:
I can take pictures of the boards.
Yes, please!

-- Jeff

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Tue Jan 24, 2017 4:12 pm
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I'm trying to get a copy of a paper (there were at least two - one in 1988 and an update in 1993) describing the system. But they've ended up behind a paywall. What I can say though (and I remember this from a presentation) is that the actual processor was called a MALU and consisted of up to 4 boards with 128 1-bit processors on each, for a total of 512 processors. The processors were connected in a grid with side-to-side connection so that it looked like a cylinder. Data would flow in at the top and come out at the bottom. Each processor (except the top and bottom rows) were connected to the processors above, below, left, and right (although data could only flow down or sideways), and also diagonally. With 512 processors the max performance was a theoretical 320 MFlops. Each element (the processors - actually I now remember they were called S-elements) supported 32 instructions, IIRC.

But I don't know how the three sets of bitslice processors came into the picture. I hope to figure that out when or if I can somehow get a copy of those papers I mentioned. A co-worker is looking into that for me. But it could be a part of the data preparation interface. This thing would run as a kind of vector processor connected to a host computer. The first version of the host was a Norsk Data ND-5700 32-bit mini, a later version used a Silicon Graphics computer - not sure which, for some reason I'm thinking Crimson, but I only remember a fancy-looking (as in Star Trek) contraption with lots of red levels and lights. In any case, there would be some interface circuitry. I have a small board here which was part of the SGI interface.

Will try to take pictures tomorrow.


Tue Jan 24, 2017 5:18 pm
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No pictures today, unfortunately - I can't find my DSLR battery charger, so it'll have to wait a bit.

I found some information about how the bit-slice processors were used. The computer had 32MB of common main memory, but the 'near' memory was 3 x 2MB dual-port static RAM, called 'BUF'. There would be one 'BUF' for every board, i.e. with 4 x 128 processors that would be four BUF modules. The bit-slice processors, six of them in groups of two can then be thought of as 3 32-bit bit-slice processors. This is called 'TRAP', fopr 'TRiple Address Processor', and the single paragraph where this is mentioned says "Three bit-slice processors, each generating a specific sequence of addresses for its BUF module. Each address processor is programmable for different addressing algorithms, e.g. data stored with fixed increments or FFT bitreversing."

So your guess about indexing wasn't too far off I guess.


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hwmodules.png
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Wed Jan 25, 2017 3:55 pm
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