Indeed, FFs, slices and LUTs are all measures of the cost of the design in terms of resources on the FPGA. FFs are the state and LUTs are the logic, whereas each slice contains a number of both of those, and might be partially used. Different FPGA families have different LUT designs and different slice designs, so the counts of these may not be comparable across families, but within a family we can compare the cost of implementations by using these counts.
EAD is a pipeline stage: it's the stage which deals with the optional operand word, which either gives an Effective Address or gives some literal Data. (I think one could instead call it the Operand stage.) See this post for more on the pipeline:
viewtopic.php?p=3026#p3026Edit: sorry about the obfuscation!
Edit: perhaps EAD is best described as a system state, not a pipeline stage.