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 7 bit Homebrew CPU Designed for Functional Programming 
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Joined: Sun Oct 18, 2015 6:53 pm
Posts: 5
Two years and still in the making...

FunCPU is a seven bit homebrew processor with unique, unconventional design to natively support functional programming in machine language. It employs a tagged architecture, it does not have registers, of which contents are exposed to the programmer. It has three built-in functions (increment, decrement, if-then-else), and another 32 user-defined functions can be entered. It has 256 bytes of memory, it supports 7 bit numerical integer precision. Despite its simplicity FunCPU can be considered a fully fledged computational device in a sense that it is Turing-complete.

Here is the project log, enjoy: ... ed-to.html

Sun Oct 18, 2015 7:03 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1419
I like it! Please could you illustrate with a simple program?

Control panel overview: ... panel.html
Video: ... sions.html
Architecture: ... ncept.html
Defining addition: ... cates.html
Computing 1+1: ... ng-11.html

Sun Oct 18, 2015 8:17 pm

Joined: Sun Oct 18, 2015 6:53 pm
Posts: 5
The ALU and register modules are still being tested. The micro-sequencer has not yet been completed, not even started, althought it has been designed. Basically, this is the only component, which is missing, no big deal, just a couple of chips. But still as this is a dynamic component as opposed to the static ones, e.g ALU and register modules, I expect to face difficulties to get this done. Not to mention the whole integration, when every module is connected and FunCPO goes live. Once everything is ready I will be giving some video tutorials similar to the one on entering expression. Thank you for your patience.

Mon Oct 19, 2015 4:40 pm

Joined: Sun Oct 18, 2015 6:53 pm
Posts: 5
FunCPU V2 is working now. Had some issues with version 1.

Some videos:

Simple expressions:

Simple functions:

A little bit more sophisticated functions:

Mon Nov 27, 2017 7:37 pm

Joined: Thu Apr 04, 2019 6:20 pm
Posts: 22
cute design! love to see more info on the hardware implementation!

Tue Apr 09, 2019 11:59 pm

Joined: Sun Oct 18, 2015 6:53 pm
Posts: 5
Thank you for the kind words.

Here is the front panel as it was originally planned:

Here one can see the modules scattered all around of version 1.

It was my first attempt, and resulted in a rather chaotic design and implementation. It is needless to say that it was not working. It almost worked, but not quite.

I created a new version. Version 2 had to be rebuilt it from scratch, using a little more reliable and disciplined approach. Here is the register module of the second build:

It is constructed from four modules plus the control board, using 74HC components and 4 EPROMs (3 used for micro-sequencer and one for the tokenizer for the tagged architecture) and one 32K SRAM.

The modules are stacked one on another. They are interconnected via 3 buses each with 40 pins.

Here one can see the stacked boards. Please notice that testing can be done just by looking at the 120 exposed pins. These pins more or less describe the full behaviour of the CPU at any moment in time.

Approximately 30 ICs were used for the CPU itself, and another 15 ICs were required to implement the interface. (These 45 components include the ROMs and RAM as well). This is needed to communicate with the CPU, i.e. to enter and read data.

Wed Apr 24, 2019 5:32 pm

Joined: Thu Apr 04, 2019 6:20 pm
Posts: 22
love the front panel!!!

Wed Apr 24, 2019 8:28 pm
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