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 ben's20 bit cpu. 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
I am posting here, so one can find it notes about my 20 bit cpu.This will be a realistic design with a front panel and blinking lights, rather than a 8 bit design with clever tweeks to address more memory. Character adressing, and a modest instruction set, required expanding a byte from 8
to 10 bits. This gives me 18+ bits true addressing,with out needing a MMU, and resonable
floating point format in software.

I have finished the fpga version with the basic serial loader @ 2400 baud.
The new Bitstream is saved, to the eeprom, so now I can work on hardware
testing and software bugs going from 18 to 20 bits.
About 30 chips will be used for the CTL section with 1973 techonlogy.
Using larger proms will save only two chips.A few chips more for a extended
cpu with excess 3 math.
Still 37 chips for the ALU section. Extended features could add 10 more chips
to the ALU section but that is for a later date.
The FPGA version is set for 1.5 us core memory cycle, but the TTL version
is expected to run with a 1.4 us core memory cycle.
Having added BIT ( r = r & ~ n) I now FEEL I can compete with the the PDP 11
had I developed this back then. Forget UNIX run BENX. Small Size,Byte addressing, index/stack registers not in CORE, Bit set/clear and a clearly defined memory/io bus, I belive are the features that made the PDP 11 a powerfull computer and I have all those features.
Now I just need a fuit type name label my computer brand.:)


Mon Nov 18, 2019 6:59 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Opcode matrix, 6800 like cpu but with core memory
Code:
   20 bits / 10 bit bytes

  +--------------------------+
  |cX:ooo:aaB:xx+:###:###:###|  -+ 512  mem
  +--------------------------+
  +--------------------------+
  |11:11o:aaB:xx+:###:###:###|  -+ 512  store
  +--------------------------+
  +--------------------------+
  |1X:110:000:xx+:###:###:###|  JSR
  +--------------------------+
  +--------------------------+
  |1X:110:000:xx+:###:###:###|  JMP
  +--------------------------+
  +--------------------------+
  |00:ccc:00i:+##:###:###:###|  BCC n*2
  +--------------------------+
  +--------------------------+
  |00:110:000:000:000:000:000|  HLT
  +--------------------------+
  +--------------------------+
  |00:111:001:0E0:000:000:000|  EI/DI
  +--------------------------+
  +--------------------------+
  |01:ccc:00i:+##:###:###:###|  SCC
  +--------------------------+
  +--------------------------+
  |10:110:aa0:xx+:###:###:###|  LEA
  +--------------------------+
  +--------------------------+
  |10:11L:aa1:SC :   : ##:###|   SHIFT -1 to -20
  +--------------------------+
   X  0 Immedate      1 Indexed
      op        aa      xx      ccc
   0  sub/sbc   jmp     z       False
   1  add/adc   a       a       Z
   2  ld        x       x       S
   3  adx       s       s       S+Z
   4  and                       C
   5  or                        -
   6  xor                       True
   7  bit                       -


Mon Nov 18, 2019 8:07 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
I have now included the prom listings. Looking at the price of real proms and programing
I may remove the ALU prom and change the alu opcodes around using ttl for alu decoding.
I suspect I need about 3 more chips and some prom changes.


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Mon Nov 18, 2019 6:51 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
I have encoded the alu better for Algol like instructions, because that was the trend in the early 70's.
I have two spare opcodes, to use for something. The hardware has the mods updated
and seems to work.
Code:
   
                   op 0/4     aa      xx      ccc
                0  sub/imp   jmp     z       False
                1  add/eqv   a       a       Z
                2  sbc/ld    x       x       S
                3  adc/and   s       s       S+Z
                4* ---/---                   C
                5  adx/st                     -
                6  xor/or                    True
                7  bit/st                    -
                *  reserved


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Tue Nov 19, 2019 3:02 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Fixed a copy and paste bug in the alu lookup tables. Added ldc (load compliment)
and stc (store compliment) to help with logic operations.


Tue Nov 19, 2019 6:55 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Debugging the 18 bit version timing issues now and I later hope to port the FPGA fixes to the 20 bit cpu.


Thu Nov 28, 2019 2:56 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
I seem to have the timing bugs and race conditions solved for now, and moved to a faster clock. 1.25 uS for a memory r/w cycle with a 8 mhz clock. Will be working on software floating point and other romable routines like free and malloc this month, then back to writing a small os, all in 32KB of core +
2 KB or 4 KB rom. I hope to have a PDP/8 syle machine, with a simple non swapping OS and a compiler floating point but no structures with around spring of 2020. Gone back to the smaller alu version.


Fri Dec 13, 2019 6:59 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Revised the 18 bit cpu to handle MOS style memory with a 5 clock memory cycle. 1.8 Mhz using 200ns memory about 1978/1979. 18.432 Mhz clock is used for timing and easy baud rate clock. Only 1KB of prom used for now. This is about as fast as 74 LS will go. Using 74 S logic give me a 2.4 Mhz clock. Using 22v10's and 74F logic (1983 ish) I can get about 4.8 Mhz clock with 70 ns ram/prom/eprom?.
(5x faster than the PC at the time). New development on the 20 bit cpu will be using 5 2901's and CMOS 22v10's + glue. (1983 time frame) for easy PCB 's.


Fri Dec 20, 2019 11:59 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1430
Nice idea to be tracking the vintage of the technology you are using and correlating it with clock speed and eventually with performance. You should, I hope, see some performance from having a wider machine (both for wider memory and for wider arithmetic ops) and possibly from having resources for more registers.


Sat Dec 21, 2019 10:36 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Clock speeds really have not changed for small memories since about 1985. What has changed
is chips have got larger so you don't need to go off board to access stuff, thus time lost with buffers
and chip select is now removed. Because of this, projects built using TTL will be still be 3 MHZ or less
in clock speed, compared to using a off the shelf cpu at 300 MHZ bus speeds. I have 1984 IBM AT speeds about 1979 but can get no faster than that with simple design 2 board CPU. For now will be the current speed so I can keep simple PCB layout, and bus. A second AC is added so floating point software will be a bit faster.I have good DOS style machine, but that is as far as I want build at this time.


Sat Dec 21, 2019 8:36 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
** IT LIVES **
I found a typo in my SD card routines, that has been in there for at least the
last 10 years. The master clock divider was getting the wrong input. Now having
a reliable I/O I can work on other stuff.
SMALL c Version 1 is now working on my computer
with a not so small OS, 16 Kb for the O/S 32Kb for programs. Stll need to port
a assembler and text editor.
The final thing I need is good name for the computer running
at core memory speeds in FPGA. ~ 1.3 us memory cycle.
Ben.


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Mon May 18, 2020 2:01 am

Joined: Wed Nov 20, 2019 12:56 pm
Posts: 35
oldben wrote:
** IT LIVES **
I found a typo in my SD card routines, that has been in there for at least the
last 10 years. The master clock divider was getting the wrong input.


Nice work!

(Don't you hate it when subtle bugs lurk for ages? I recently had a similar situation where a 0xff00000 written years previously should have been 0xff000000 - it was causing failures to read from SD card but only in very specific circumstances!)


Mon May 18, 2020 9:27 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
I now have both 20 bit and 32 bit cpu, with a bootstrap dos.
and can run "hello World" programs from disk. The joys of updating two versions
software. Both use IBM 2310 disks and packed with core memory around 1974.
A mos memory version out around 1976.
Ben.


Fri Jun 05, 2020 6:52 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Core memory lives again. Timing is set for a .75 us clock and a 1.5 us memory
cycle with a simple timing model using static ram. I plan to be write floating point
software and get my compiler cleaned up this month. Next month get the DOS debugged
and write a simple line text editor, and port the software written C
(assembler/compiler/microcode compiler) so the system is self hosting.


Wed Jun 10, 2020 10:06 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
Detailed look at the logic, shows I have very little margin with the clock from the orginal
design. Feature creep added 60 ns to the data out path bringing me to 460 ns for
500 ns clock. I am guessing 30 ns for clock skew from the master 4 Mhz clock,passing
thru a D F/F and a clock buffer,giving me 10ns margin. Going to a 3.68 mhz I get .813 us
clock cycle and can sleep better with another 20 ns margin.
Ben.


Fri Jun 12, 2020 8:15 am
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