In this post I describe the operation of the Master and Slave shift registers.
I found that there was very little practical information on the 74xx299 online, as mostly other shift registers such as the 74xx166 and 74xx595 are covered as various Arduino I/O extenders.
The 74xx299 is a universal 8-bit shift register which supports a parallel 8-bit tristate I/O bus. It has serial inputs and outputs that support both serial loading either in a left shift or right shift direction.
As such it offers parallel to serial and serial to parallel conversion, in a single device which is compatible with a typical 8-bit microprocessor bus.
The NXP datasheet is here, which shows the internal structure. Note that the NXP pin names are slightly different to those I have used which were from TI.
https://assets.nexperia.com/documents/d ... 4HC299.pdfAs a convenient analogy, in one respect think of it as a single 8-bit storage register, which can be written to or read back from - but with the added advantage that it can exchange data with other devices over a serial link.
The 74xx299 has 4 modes of operation, controlled by the S1 and S0 pins:
0 0 HOLD (STORE)
0 1 SHIFT LEFT
1 0 SHIFT RIGHT
1 1 PARALLEL LOAD
In addition, it has two active low tristate controls G1 and G0. Taking either of these high will put the output pins into high impedance mode, allowing tristate operation on a bus. When parallel load mode is selected with S1 and S0 both high, the bus pins are automatically put into high-Z mode, allowing data to be loaded from the bus.
There is an active low asynchronous clear, which will reset all the internal flip-flops.
For accessing the serial data, there are two inputs SL and SR for accepting serial data for left shift and right shift modes, and two serial outputs QA' and QH' which give a direct (non tristate) connection to the first and eighth internal flip-flops.
On a single clock input, data is shifted on the rising edge of the clock.
With all these pins, it took a bit of figuring out how best to control the device using signals that are compatible with the familiar SPI bus. To simplify the problem, I decided to adopt a left shift convention, but equally right shift would be equally applicable, as the internal structure of the shift-register is entirely symmetrical with no preference to either mode.
In left shift mode, serial data will enter via the SL input pin (18) and be shifted out lsb first through the QA' output pin (8).
To connect two registers together in a master-slave configuration, the QA' of the master is effectively MOSI and connects to the slave SL, and the slave QA' is MISO and connects back to the master SL pin.
The first diagram shows the basic connections for master-slave operation using the standard SPI signal naming conventions.
Attachment:
master_slave_1.jpg [ 72.05 KiB | Viewed 5030 times ]
In this configuration the contents of the master will be transferred to the slave, and the slave contents simultaneously transferred to the master by applying 8 clock pulses to the SCK line. Performing this circular transfer of data between devices is the basis of SPI communications.
All it needs is a shared clock line, two signal lines for full-duplex operation and some means of enabling the slave device.
Compared to the complexity of asynchronous serial communications involving UARTs, baud rates, handshaking, parity, start and stop bits, voltage level converters, synchronous serial communications is a breeze.
With modern HC TTL, clock frequencies of tens of MHz are possible. At 5V supply the 74HC299 (NXP) has a maximum clock frequency of 50MHz, well above the speed requirements of a classic microprocessor bus.
When I first learnt this behaviour of shift registers some 35+ years ago, I was fascinated that such a useful function could be obtained from such a relatively simple device, even more so when some years later when it became the fundamental operation behind SPI.
Below is the test circuit that I have been simulating using H. Neeman's "Digital simulator". I have added push buttons for convenient manual loading of the register and LEDS and 7-segment displays to indigate the contents of each register.
Unused input pins are shown with the square symbol. During simulation thes pins default to logic zero.
I have created a new Github repository for this exploration:
https://github.com/monsonite/SPI-MasterAttachment:
Master_Slave.jpg [ 169.09 KiB | Viewed 5030 times ]