All my testing seems to indicate that I have indeed managed to get it working!

The first benefit is that the bypass selection is no longer performed at the beginning of a cycle, where it would have selected from pipeline registers at different stages, but rather at the end of the cycle to clock the (potentially bypassed) value into the pipeline register. That way, the next stage has an immediate access to the correct value, and the bypass selection logic is now entirely out of the critical path.

The second benefit comes from moving the logic one stage earlier, as I wrote in my previous post, and having it apply directly to the pipeline registers, meaning that the value is always the result of the previous (or second previous) instruction. If there is a multiplication that needs multiple cycles in the Execute stage, the next instruction waits in the Decode stage, where the bypass logic gets updated "for free", until the result of the multiplication is ready.
Well, except that I haven't implemented the multiplication yet

Short update to say that the project is not dead !

Progress is slow with life getting a bit in the way (and also #toomanyhobbies), but I'm still working on it.

I am still in the circuit design phase in Digital, currently working on three main tracks:

First, the CSRs and support for traps (Exceptions and Interrupts). Still not everything is entirely clear in my mind, but I feel I'm getting there.

Second, it looks like I have managed to build a 4-bit (for now) Radix4 Booth Multiplier with support for Signed and Unsigned operands. Sign is handled by simply expanding each operand to 6 bits, either with 0's to treat it as unsigned, or with the original sign bit to treat it as signed. It is expanded to 6 bits, not 5, because the Radix4 needs an even number of bits. I still have to expand it to 32x32 bits, and then see how I can integrate it in the pipeline. I'd also love to make it fuse pairs of MULH/MUL instructions so that the second instruction can just output the low 32 bits of the result computed previously!
In any case, this exercise definitely confirmed that I'm not good at converting state machines into actual circuits, this made me struggle quite a lot!

Finally, I have also started the long work of converting the whole design to something that looks more like actual available components in the 74 series, in preparation for the build. A good part of that is moving to buffers with an active low Enable signal, and that has repercussions in most of the logic because I don't want to just slap an inverter in front of it I'm reworking some combinatorial logic clusters as well, since the [A]LVC family provides 3-input AND and NAND gates, but no 3-input OR or NOR gates, for instance.

I'd also like to build some test circuits soon (for very large values of soon, possibly) to test the speed of the Adder and the Magnitude Comparator I intend to build. My feeling is that the adder speed will have a non-negligible impact on the final clock speed.

Have a GOOD power supply.
Figure out your bus , memory and I/O at this time. While not RISC, a 8 bit IO bus, will let you run slow I/o chips,
like uarts and timers.

The best I can do is about 3 Mhz for memory,1 Mhz for serial IO. (6502 memory cycle).
Part of the reason is clock oscillators only come in a few frequencies.

Design your PCB's as 4 layers. This lets really save space with the bypass caps on the vcc/gnd planes.
Plan to have a CASE and fans too keep things cool.

I picked up a 10 watt laser cutter/engraver so I could make a easy box for the case for my current computer design.
Source bulk known parts now, like bypass caps and sockets.
I get many parts from china (ebay) and you have 2 month delay with shipping.
Have a GOOD power supply.

Thanks a lot for your comment. It is always appreciated, especially when it confirms that I need to be careful about something.

I am indeed working on the memory bus (still everything simulated in Digital). I already have a "fast" SRAM interface directly accessible in a single clock cycle and a slow EEPROM interface that will read one byte at a time and latch them each to make a complete 32 bits word. These two are already present in the simulator.
What I want to add is a somewhat generic access that will respect the timings used for things like ISA or ATA PIO modes.
The design already supports byte, 16-bit halfword and 32-bit words access by way of setting four ByteEnable signals and shuffling the data as needed to match it with the least significant part of the register. I do not intend to support non size-aligned accesses.

I expect the project to be unreasonably large, spanning multiple PCBs, even using SMD components. Most of it will likely run on 3.3V (LVC), with some sections on 2.7V to stay in the safe zone for the AUC family components. Some other parts may be 5V. And since I'll be playing with pretty fast edges, I fear that 4 layer will be the strict minimum, if only to keep the ground plane close enough to have a good return path and controlled impedance. I already suspect some boards will need 6 layers. 32 bits data and 32 bits addresses make for a lot of wires!

As for the power supply, I think an ATX power supply should do the job and give me plenty of power on the 3.3V rail. It will be either that, or Meanwell power supplies. But more important, I hope I'll get the power distribution right as well! For bulk power caps on the boards, I have a stash of 680µf Aluminium-Polymer capacitors that I bought by mistake for a previous project, I think that should do. For decoupling, I may try to use 1µF MLCC caps instead of 100nF, because I read that article https://codeinsecurity.wordpress.com/20 ... nf-behind/

I'll try to find a 19" subrack for the case.

Don't forget to add a write enable switch on the EEPROM. It looks like you have it all covered,