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 Octal computers 69+ 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1846
Nice!


Tue Sep 30, 2025 6:47 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
Thank you.
I got in the new 5V power supply and it is 50% bigger than the old one, and POWER to spare.
Testing now a .750 uS clock cycle.

Ordered parts for a .650 uS clock cycle, the design limit for this computer.
This includes bigger bypass caps.
Now In the ballpark of PDP-8 memory speed here.
Most of my time will be now on software and mico-code revision.
I want to see if I can do simple 36 bit design and that means limited character operations. The current design
was designed more for Small C.


Sat Oct 04, 2025 3:27 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
oldben wrote:
Thank you.
I got in the new 5V power supply and it is 50% bigger than the old one, and POWER to spare.
Testing now a .750 uS clock cycle.

Ordered parts for a .650 uS clock cycle, the design limit for this computer.
This includes bigger bypass caps.
Now In the ballpark of PDP-8 memory speed here.
Most of my time will be now on software and mico-code revision.
I want to see if I can do simple 36 bit design and that means limited character operations. The current design
was designed more for Small C.


Things have got too messy,so I need to start fresh. A 1.00 uS clock or .868 uS clock is planned.
I am short a few 16 pin sockets so I plan to chop down some 20 pin sockets. This will keep me busy over
the week end, as I build new pcb's,


Fri Oct 10, 2025 4:39 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
I found some lose 16 pin sockets, so I got the cpu board made.
Timing is .918 uS, for a 1.8 uS emulation. Faster may not work, so
need more testing. .833 uS is the next trial. Revised the order code to have ,Read Switch Register,
and made the PC (p) a valid register for load. Added base registers E..L,
load store only, giving more a 1960's feel.
It may not compete with the PDP 11, but it does compete well the IBM 1130.


Sat Oct 11, 2025 6:25 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
A plcc socket cracked, so that PCB is toast.Testing using the other hacked PCB.
Gone to 4.77 Mhz, for PC speeds :) This build seems stable so far.


Mon Oct 13, 2025 10:02 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
Found a 4.9Mhz oscillator, in my junk box and now testing with that. Removed the pc as valid destination. The irq service call, now jams 007000,2 into the IR, and state counter,permitting a push of the pc on the stack,


Wed Oct 15, 2025 8:35 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
Back 4.77 Mhz. Gone to 504 sectors of 768 bytes, for 378Kb 8" floppy with a simple FAT file system. ~8 Kb used for file buffers and 8Kb for stack. EEProm is Kb and 8Kb expected for the Shell. 32 Kb used just for a floppy OS. Another 8K is needed if I use a 1 Mb hard disc. 192 x 2 heads x 4 sectors.
.


Wed Oct 22, 2025 5:08 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 2406
Location: Canada
768 byte sectors is an interesting size. Is that including space for a preamble? Formatted sectors are often a power of two.

_________________
Robert Finch http://www.finitron.ca


Thu Oct 23, 2025 5:59 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 853
The SD card routines read/write standard 512 8 bit bytes per block. That gets gets converted internally to read 256 x 9 bits.
1 Kb sectors work just a bit better for a simple 1 block directory over 768 bytes per block. Now I can have 8.3 file names rather than
7.2 file names.
Looking for Rat C compiler source (A C compiler 1st ed).
Also looking for a simple file system algorithm.
Not having a compiler is big problem.


Thu Oct 23, 2025 5:24 pm
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