Another update for the Tridora-CPU - it now has a data cache in addition to the instruction cache.
This has a noticable impact on compile times: building "hello,world" now takes 15 seconds instead of 20.
As with the instruction cache, it just caches the 16 bytes that the DRAM controller always delivers. Since with the stack machine architecture you often read, write and read the same location again, it was important to implement it as a write-back cache. Otherwise the cache would be invalidated too often.
Thankfully, the write-back mechanism was not as complicated as I feared.
I have updated the benchmark results at
https://gitlab.com/slederer/Tridora-CPU/-/blob/main/examples/benchmarks.results.text. If you compare the performance when running code from DRAM without any caches to the current version, you get a three times better performance in the empty loop benchmark.
In comparison to running without data cache but with instruction cache, you get 1.6 times better performance.
The other big thing is this update is the audio controller. I finally hooked up the Digilent AMP2 PMOD and added something like the sound generator chips of the early 1980s to the logic design: Four channels of rectangle waves and a noise generator. Then I thought, that is boring, and reworked it so that now it can to interrupt-driven sample playback at (at least) 32KHz (mono).
Here is a video where you can hear the Tridora-CPU making noises and playing music:
https://youtu.be/p3USZ40Du24And now I guess it is already time to plan this year's christmas demo...
