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 Some Minimal Instruction Set CPUs 
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 118
You left out the 1 instructon set computers, like subtract and branch if <= 0,
or move type computers, move a to b, and jmp if <0. Here the memory does all the logic.


Tue Jan 14, 2020 9:48 pm

Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
The Anitra Computer
    A Complete Minimalist Computer System Designed, Built and Programmed at a Low Level of Abstraction
    A hobby electronics project by Eirik Bakke (2004).

https://people.csail.mit.edu/ebakke/anitra/article.html

An 8 bit processor with only three instructions (Mov S,Q; Add S,Q and IOX S,Q).
Each instruction is formed from four consecutive bytes in a 32K address space.
Image

Note the absence of a data path between the Data Bus and the Program Counter!

Quote:
What I could not seem to justify the need for, however, was making PC a programmable, rather than a non-programmable, counter. A fundamental operation in computer programs is to have the program counter branch to another part of the program. This would traditionally be done by having a programmable program counter load a target address from the branch instruction. This is not necessary here.


He has written a cross-assembler, a debugger/emulator and a parallel port uploader for it, as well as a Virtual Machine Emulator:-
Quote:
The virtual machine is far more advanced than Anitra itself, with 14 instructions, in-built function calls, separate data and return stacks, relative local variable addressing, unconstrained branches and so on (the instructions being JCZ, JMP, JZ, CALL, RET, PUSH, POP, LIT, SEG, LOAD, STORE, ADD, COM, and NOP). Although at a cost of speed, this allows Anitra to be programmed without any of the initial limitation on code size, branching etc.


P.S. He also did a Four Instruction Computer that ran on a Spartan-3 Starter Kit:-
https://people.csail.mit.edu/ebakke/fic/
(A possible entry for the One Page Computing?)


Last edited by BigEd on Thu Jan 23, 2020 8:13 pm, edited 1 time in total.

fixup image link



Thu Jan 23, 2020 8:05 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1430
Thanks - some very interesting ideas in there. Like the gigatron, building a simple machine then implementing a more comfortable machine on it. Here's how the short unwriteable PC works out to be useful enough:
Quote:
The Anitra computer has up to 32Kb of memory, divided into 128 256-byte segments. Full memory addresses consists of a near address and a segment number, denoted as from [0:0] to [127:255]. Executable instructions must be placed in the first two segments. Each instruction takes 4 bytes, making 128 instructions available for machine coding. The instructions will be executed sequentially in an eternal loop, returning to start after the last one. The first two segments are organized in 16 blocks of 8 consecutive instructions each. Branching from an instruction is done by skipping the remaining instructions in the current block, or when branching from the last instruction in a block, by skipping the complete following block.


Thu Jan 23, 2020 8:26 pm

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1137
Location: Canada
Wow! Awesomely minimalist computer. Well thought out. I wonder if the program counter could be eliminated by using more memory to store the next program address in each instruction.

_________________
Robert Finch http://www.finitron.ca


Fri Jan 24, 2020 7:47 am WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1430
B.Bibby wrote:
P.S. Eirik Bakke also did a Four Instruction Computer that ran on a Spartan-3 Starter Kit:-
https://people.csail.mit.edu/ebakke/fic/
(A possible entry for the One Page Computing?)

Oh, another good find! And yes, the Verilog fits on a page. Indeed, it was a goal:
Quote:
Its design is simple enough that it should be possible to implement it with less than a page's worth of Verilog code.

And once again, the four-instruction machine supports a virtual machine which is more comfortable.


Fri Jan 24, 2020 8:43 am

Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
Mark’s TTL Microprocessor

From Web.Archive, Circa May 2006 :-
https://web.archive.org/web/20060508015602/http://home.inreach.com/~jamesc/ttl/
Quote:
It works! My TTL microprocessor has:
-5 instructions
-16 nibbles RAM
-4K program memory

The design is 8 chips, not including RAM and ROM. Without using the two PALs I used, it would be 16 chips.

The goal was to make this as stone-simple as possible because ANY feature creep will snowball into a totally different architecture. For example, just making it 8-bit would require a board 8 times larger, not twice. Same thing if I wanted more than 4K code, or if I desired more than 16 nibbles of RAM (which would be unadressable by this uP). The instruction set was whittled down as much as possible while still retaining some usefullness, as opposed to some even smaller designs I've seen where there isn't even provision for I/O (so how do you know it works!) My uP has one 4-bit input port and one 4-bit ouput port, which are mapped onto the 16th nibble of RAM.

Alas, the images seem lost. But fortunately absf(Allen) on the AllAboutCircuits.com Forum made a version of it and has a few pictures:-

Quote:
I have constructed a 4 bit TTL cpu with the help from the designer. His web site only gave the block diagram of his cpu. So after a few weeks of emails Q&A, I finally got the cpu working executing a simple program flashing some LEDs.

His original design used 2 PAL chips and 5 TTL chips but in my design I used 15 TTL + 2716 EPROM and 2114 static RAM chips cause I dont have a PAL programmer. IIRC, the site was called "Mark's TTL microprocessor".

The control unit was nothing more than just logic gates and a 74LS138 decoders.

After a few weeks and numerous emails with the author, I finally got it to work.

Quote:
It doesnt have an dedicated ALU. The concept is very simple. It has an Accumulator, a 12 bit program counter able to address 4K memory , 16 nibble RAM and only 5 instructions.

-lda load accumulator (RAM or immediate)
-inc increment accumulator
-jmp jmp to new location
-cse skip next instruction if acc=data in RAM.

There is no stack, no subroutine call and no arithmetic instructions.


Image
Image
Image


Fri Jan 24, 2020 11:48 am

Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
A 1 bit One Instruction Set CPU with no ALU, and implemented with roughly 650 transistors on thirteen PCBs.

Image

http://mircad.com/q/index.html

Quote:
Qibec (pronounce "Quebec") is a simple educational CPU - not a complete computer - made from discrete transistors.

This CPU (Central Processing Unit) only has 1 single native instruction, which operates on 1 data-bit.

Image

The one instruction is an “Invert and branch if clear”, uses 16 bits for addresses, with 32 bit instructions (branch address + data address) in ROM.

Image

https://www.youtube.com/watch?v=nqpdOWwthcA


Sun Feb 23, 2020 11:37 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1430
That's quite nice! It may seem uncomfortable - but with the macro assembler, one can build up a more useful instruction set, which is a good lesson. I see it's been presented as an educational tool: see the playlist and also see the second version:

http://mircad.com/q/programming.html
http://mircad.com/q/videos.html
https://www.youtube.com/watch?v=klVOlyDpr1U


Mon Feb 24, 2020 9:16 am

Joined: Sun Oct 18, 2015 6:53 pm
Posts: 5
I think my so-called FunCPU also qualifies as a minimal instruction set CPU. It has three basic operations and nothing else (except for function calls). These are as follows:
- increment a value by one
- decrement a value by one
- if-then-else construct, i.e. if <condition> then <expression1> else <expression2>

More information on this:
http://funcpu.blogspot.com/2014/04/func ... n-set.html

Some notes on the computational model:
http://funcpu.blogspot.com/2014/04/func ... model.html


Mon Feb 24, 2020 8:39 pm

Joined: Wed Mar 18, 2020 7:04 pm
Posts: 1
With 21 instructions my NanoCore design should qualify as a minimal instruction set CPU:
https://sites.google.com/view/m-chips/nanocore

And the computer I built around it to prove it could do some real-world stuff:
https://sites.google.com/view/m-chips/cpld-5

Image

Its great to see all these minimal designs :D


Wed Mar 18, 2020 7:16 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1430
Excellent! (Simple 8 bit machine with 16 bit address space fitting in a 95144 medium size CPLD)

And welcome!

(BTW, your 'image' link isn't working as an image, but it works for me as a link)


Wed Mar 18, 2020 8:46 pm

Joined: Wed Apr 24, 2013 9:40 pm
Posts: 188
Location: Huntsville, AL
Very nice. Thanks to all for sharing your designs on this thread. I have certainly enjoyed reading about them.

_________________
Michael A.


Thu Mar 19, 2020 10:14 pm

Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
For any of you that missed this one on Hackaday, a one instruction set computer (byte-byte-jump) built from memory chips:-
https://hackaday.com/2020/02/20/a-turing-complete-cpu-from-ram/

It is built from five memory devices using these parts:-
    1 SRAM
    4 EEPROMs
    2 pullup resistors
    4 LEDs w/ resistors, to provide blinkenlights for each signal
    and about 40 wires
Image

The SRAM is the heart of the “processor”, and the four EEPROMS are pre-programmed with the bit patterns for controlling the SRAM. Although it does use a Raspberry Pi to program it and serve as an I/O terminal.

It takes about 200 clock cycles to execute a single byte-byte-jump, around 200 byte-byte-jump instructions to execute an 8-bit addition. In the video below, it is running a Fibonacci program, and the output of the first few numbers can be seen on the monitor behind.
https://m.youtube.com/watch?list=PL4Aym2GNCg4hb7xvSkjSgP3m2xWIY_TZK&v=czqaxWhnxVw#

For a description of how it works (and a little history), see the author’s website:-
https://mysterymath.github.io/simple_cpu/ and
https://mysterymath.github.io/simple_cpu/details.html


Thu Mar 26, 2020 8:05 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1430
Great - I love this kind of thing, impractical though it may be.


Thu Mar 26, 2020 8:13 pm

Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
For a very impractical MISC, a ‘Universal Turing Machine’ using about fifteen TTL chips including a pair of 2102 RAMs for the state machine program and data tape.

https://archive.org/details/byte-magazine-1976-12/page/n115/mode/2up

“A one state Turing machine program to clear the tape has two instructions”


Sun Jul 05, 2020 10:04 pm
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