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 Ferranti's 12 bit wonder: the 1968 FM1200 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1166
This is a bit of a placeholder post as I haven't found out much about this machine yet.

It's notable that Ferranti made a successful series of 24 bit minicomputers so I'd expect this 12 bit machine to be related in some way, as a cost reduction and perhaps some family resemblances. In fact it's looking like an aviation machine, so reduced weight (and perhaps power) is going to be important.

Some snippets from searches:

Quote:
Aeroplane and Commercial Aviation News - Volume 116 - Page 32
https://books.google.co.uk/books?id=YFApAQAAIAAJ
1968 - ‎Snippet view - ‎More editions
Quote:
As well as its established range of Decca Navigator systems and equipment, including the Omnitrac computers ... Production models are expected to be available early next year of another new Ferranti machine, the FM1200, which was ...

Quote:
Interavia - Volume 23 - Page 1088
https://books.google.co.uk/books?id=cXwkAAAAMAAJ
1968 - ‎Snippet view - ‎More editions
Quote:
Ferranti. The Digital Systems Dept. will be exhibiting an FM 1600B general purpose, realtime digital computer which is the ... weight and cost. compute the new FM 1200 microminiature housed in a hall ATR case, and mulli-la\e: - cuit boards.

Quote:
Scientific and Technical Aerospace Reports - Page 1300
https://books.google.co.uk/books?id=hi60IQnfa20C
1969 - ‎Snippet view - ‎More editions
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... format instructions, parallel arithmetic. floating point number representation, a large instruction set, longer word length, and more sophisticated software. ... arithmetic codes and, in manned missions, inflight maintenance Author (ESRO) N69-18598; Ferranti Ltd. Bracknell (England). ... proposed has since been used as the basis of a new computer, the FM 1200, intended for aerospace applications.

Quote:
Scientific and Technical Aerospace Reports - Page 408
https://books.google.co.uk/books?id=Zm_oSIuwrA8C
1971 - ‎Snippet view - ‎More editions
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The problems of input and output control are discussed and the Ferranti S interface developed for use with the FM 1200 computer is described. Reference is made to the use of sensor processing techniques as opposed to central computing.

Quote:
Bulletin signalétique 890: Industries mécaniques génie civil. ...
https://books.google.co.uk/books?id=oDVXsQm1dkAC
- Translate this page
1972 - ‎Snippet view - ‎More editions
Quote:
General review of computer systems and outlook for the future. A. G. A. R. D. Conf. Proc., Fr. (1970), n° 68, 1-1.9, 2-2.6, ... Problèmes des interfaces ; cas du calculateur Ferranti FM 1200. Tâches de guidage et de navigation réalisables par ...
(See also https://books.google.co.uk/books?id=ZLboAAAAMAAJ)

Quote:
Jane's Weapon Systems - Page 1022
https://books.google.co.uk/books?id=GHYSAQAAMAAJ
1985 - ‎Snippet view - ‎More editions
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Note 7978 1416.063 IP 08C Computer 1973-74 1334.453 DUBV-43 Variable Depth Sonar 724 1417.063 Camilla Computer ... Type SMR Computer 1973-74 1342.353 Ferranti Seaspray Helicopter ASV Radar 584 1425.063 Type SM-3 Computer 1973-74 1343.321 ... 400 Computer 1971-72 1347 353 Type 601 Infra-Red Linescan 1971-72 1430.063 FM 1200 Computer 1971-72 1348.331 R550 Magic ...


Tue Mar 12, 2019 10:13 am
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Joined: Tue Dec 18, 2018 11:25 am
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Location: Hampshire, UK.
There’s some detail on the Ferranti FM1200 on pages 23 and 24 of this PDF from AGARD (Advisory Group For Aerospace Research & Development):-

https://www.sto.nato.int/publications/AGARD/AGARD-CP-68/AGARDCP6870.pdf


Tue Mar 12, 2019 11:45 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1166
Oh, that's a great find - thanks! Contains the paper
TRENDS IN THE APPLICATION OF DIGITAL COMPUTERS TO GUIDANCE AND CONTROL
by
W.H. McKinlay, M.A.V. Matthews and R. Wright, Ferranti Limited

Also a reference within, if we could find it, to:
Quote:
Remington, Williams, Wright "An outline of the Ferranti data handling system proposed by the Sud-Aviation Group for project L.A.S.".
Proceedings of the 1968 International Colloquium on Aerospace Computers in Rockets and Spacecraft, published by the Centre National D'Etudes Spatiales, Paris.


Tue Mar 12, 2019 12:30 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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Just to pull some quotes from McKinlay et al, in particular to highlight word length choices and serial vs parallel operation:

Quote:
The computer proposed was a small G.P., single address machine, operating in a serial-parallel mode. It had a word length of 13 bits. A short word length was desirable in order to minimise hardware, and it appeared that at least 12-bits were required to specify an efficient instruction code. The data word length used in associated scientific experiments was to be 13-bits, including parity, and so this word length was adopted for both instructions and data.
... The design was based on low-power T.T.L. logic. The central processor design used some 280 integrated circuit flat-packs, and was estimated to weigh 3 Kgms and have a power consumption of 5 watts. The speed of a basic instruction, using a 1 micro-second beat and an 8 micro second store cycle time, was about 36 micro-seconds. This was adequate to deal with the estimated computing load of 20,000 simple orders a second.

In the L.A.S. study the achievement of reliability and power consumption targets presented the greatest difficulty; the achievement of acceptable weights, costs and computational speed did not appear to be difficult.

Although the L.A.S. project was not funded, the study of a number of new aerospace and control projects, including jet-engine control and the ARINC 561 Inertial Navigator, indicated that there was a need for a small cheap and reliable computer with similar facilities to those of the L.A.S. machine, but with a higher computing power.

A minimum hardware solution and short word length were still acceptable and were desirable, not only to achieve high reliability, but also low cost.

The word length was reduced to the more conventional length of l2-bits, but the design included features to facilitate multi-length working. The required increased computing power was achieved by adopting fast T.T.L. logic (Ferranti Micronor 5), an existing fast (1 microsecond) core-store, a more powerful function code (including hardware division) and a parallel arithmetic unit. Simple orders are executed in about 4 microseconds and multiplication in 14 microseconds. The central processor unit comprises some 360 dual in-line elements and occupies 10 cms length of a JATR box.

The FM 1200 computer has been used as the basis of a number of studies of aircraft systems, including engine control in multi-engined aircraft and advanced military navigation and attack systems. In general in these systems, where the computing capacity of the machine has been approached, it has been advantageous to use multiple computer systems in order to provide reversion. These studies have also indicated that 24-bit Computations are adequate for navigation, and that there is not significant reduction in the proportion of double-length working should the machine word length be increased to 16-bits.

For a number of applications the FM 1200 is now being offered with semi-conductor memories.


Quote:
An example of an advanced input/output system is the Ferranti 'S' Interface, which has been developed for use with the FM 1200. This enables the computer or the peripheral to initiate the transfer of single words or blocks of words from the computer store. The transfer takes place serially between the buffer register in the computer C.I.E. and the peripherals, the buffer register being loaded or unloaded from the store by a parallel-transfer Data Interrupt. At the termination of a sequence of transfers a Programme Interrupt can be initiated for the data to be serviced, but until this happens the transfer proceeds effectively independently of the computer. The rate of serial transfer over the peripheral-computer highway is dictated by the peripheral and can be at a peak rate of up to 8 megabits a second.


Also of some interest for having a serial arithmetic unit but a parallel memory, the Argus 400:
Quote:
... the ARGUS 400, and we believe it to be the first micro-miniature airborne computer to be designed and developed in Europe. It is basically a re-engineered version of the earlier ARGUS general purpose computers, initially developed for the control of the BLOODHOUND missile. It is a 24-bit, "one and a half" address machine using a serial arithmetic unit and a ferrite-core memory operating in the parallel mode. The speed of the store is not fully used by the computer, and the resultant waiting time is utilised by allowing direct access to the store for input and output without loss of computing speed. The computer also has facilities for directly addressing input-output by program. Some applications of this computer will be described later, but it is of interest to note that its main airborne application has been in experimental navigation systems. This confirms our view that a 24-bit data word is sufficient for most navigational systems, and illustrates the flexibility of using a variable program store. In these applications protected volatile program storage appears to have been satisfactory.


Wed Mar 13, 2019 11:11 am
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Joined: Wed Apr 24, 2013 9:40 pm
Posts: 159
Location: Huntsville, AL
Interesting read. Thanks for pulling and posting those excerpts. The serial ALUs are an interesting feature.

The MiniCPU-S design, which I've not completed, was based on a serial ALU and PCU (program control unit). I was inspired to consider this approach after reading about the Elliot Brothers computers, and the Motorola 14500B.

Somewhere in my notes I have an article that describes a multiprocessor (Canadian in design) based on the 14500B. Over the years I would reread the article; it provided much food for thought along with Jackson's papers on serial mode DSP functions. Another interesting feature of serial ALUs is that they easily allow for triple mode redundancy.

With modern processes, a serial ALU can easily be made to operate at rates that result in very respectable performance.

_________________
Michael A.


Thu Mar 14, 2019 1:20 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1166
This is something I only realised explicitly a day or two ago: a serial ALU can avoid being a bottleneck in a system with a parallel memory if it's clocked fast enough. And since the serial ALU is small and self-contained, there is a very good chance it can be clocked much faster than an off-cpu memory bus. So, for example the 8MHz Ferranti F100-L (a 16 bit micro) isn't too far unbalanced if the memory runs at half a megahertz. And that's about right for the late 70s with semiconductor memory.

(It's not entirely unlike the Z80's nibble-serial ALU, in a 4MHz micro, used for 8 and 16 bit operations.)


Fri Mar 15, 2019 12:26 pm
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