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 Experience with 68SEC000? 
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Joined: Tue Jul 23, 2019 5:55 pm
Posts: 4
Location: Hixson, TN USA
First time poster!

I'm starting my first 16-bit project (I designed an 8-bit 65C02 computer last year). Since I plan on using some FPGA's, I thought about going with the 3v3 version of the 68K (68SEC000). Plus, they are still pretty cheap to get.

Anyone work with that chip? None of the design documents I've found seem to mention it. It has a "true" A0 whereas many documents mention that an original 68K doesn't have an A0 pin. All of them seem to use the /LDS and /UDS.

Anyway, I was wondering if anyone knew of any gotchas I should be aware of when using this chip compared to the more traditional 68K's.


Tue Jul 23, 2019 6:24 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1419
Welcome! Let's see if we can help - either way, it will be interesting to hear about your progress.

Wed Jul 24, 2019 6:39 am

Joined: Wed Jan 14, 2015 2:56 pm
Posts: 8
Location: South Wales, UK
I've not used the 68EC000 version myself but looking at the datasheet it looks like A0 is used along with the LDS and UDS lines.

During operation in the 16-bit mode, byte operations can occur on either D15–D8 or D7–D0,depending on A0. If A0 is zero, the upper byte is used and UDSB is asserted. If A0 is one,the lower byte is used and LDSB is asserted. For word and long-word operations, A0 is always zero, data bits D15 through D0 are used, and both LDSB and UDSB are asserted.For long-word operations, data is transferred in two bus cycles with A1 indicating which half of the long word is being transferred. The actual order of the long-word halves is instruction and address-mode dependent.

Wed Jul 24, 2019 10:57 am
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Joined: Tue Jul 23, 2019 5:55 pm
Posts: 4
Location: Hixson, TN USA
I haven't seen that PDF yet. I will add it to my collection and study it as well.


Wed Jul 24, 2019 12:33 pm
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