It seems I can't have exactly the combination of clocks desired. (At least not with a single clock resource).

100MHz input
200MHz ram clock
85.714 MHz video dot clock
50 MHz cpu clock
125 MHz Ethernet clock

How accurate does the Ethernet clock (ethgtx_clk) have to be in practice. It's spec'd as 125 MHz but I'm wondering if I can get away with 120 MHz. If I can get away with 120MHz then the system will be made with just a single clock resource.
Alternately, how much can a VGA clock differ from spec ? I've already got it at 85.714 MHz rather than 85.6 for spec.

Rob:

We use a separate 125 MHz clock for the Ethernet. If you use SGMII, then it will require additional multiplication. Taking a single 100MHz oscillator and using cascaded DCMs to derive the various clocks is not something I'd recommend for use with the Ethernet interface. So my recommendation would be to use a dedicated 125 MHz reference for Ethernet and a 100 MHz (or any other appropriate frequency) reference for everything else. We cross the clock domain boundary between the 125 MHz Ethernet clock domain and our other clock domain using FIFOs supplied by the Xilinx CoreGen tools.

May not help this exact case, but I found an online spreadsheet for calculating closest multipliers and dividers for specific input and output frequencies:
https://docs.google.com/spreadsheet/ccc ... ring#gid=3

For example, it says that 100MHz * 107/125 is 85.6MHz
(Are such large divisors and multipliers available in this case?)

Edit: I notice it only finds exact matches, not close ones. There must be a better way...

Cheers
Ed

BigEd:

Depending on the technology, there is generally a limit on the multiplication that can be applied such that the multiplied frequency (for general purpose DLLs/PLLs in FPGAs) must be somewhere in the range of 300 MHz to 750 MHz. Thus, with high frequency references, the multiplication and division values are generally much smaller than the values you have noted in the post above.

It may be more advantageous all around to use a lower frequency reference as it would allow more flexibility in the choice of the multiplication/division ratios. I suspect this is one of the reasons why many modern microprocessors use low frequency fundamental mode crystals backed by internal PLLs to provide their high frequency clocks. (Another consideration is, of course, the higher complexity of building reliable higher order harmonic crystal oscillators. The highest harmonic that I've ever seen successfully employed was a 7th order harmonic oscillator.)

Ah, yes, very good point that there will be an upper limit to the PLL internals. I think I've seen several FPGA boards with a 40MHz or 50MHz crystal, which fits in with what you're saying.

I hope I don't go nuts deriving timing specs.



Alas, I'm using a pre-made board which has just a single 100MHz clock oscillator for a source. I can't change the clock source or easily add another clock. The good news is the 125MHz reference may not be needed with this board (was needed for a different board), but I got to study it some more. I note there is a 25MHz crystal tied directly to the Ethernet chip, so that maybe the required reference.

Clocks in the system:
100MHz input
200MHz ram source clock
-- 300 MHz derived ddr2 clock
-- 75 MHz derived memory interface clock
85.714 MHz video dot clock
50 MHz cpu clock
?125 MHz Ethernet clock

With all the clocks in the system, I may as well add another one for RS232 timing generation.
24 MHz? Serial comm clock.