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 [ 5 posts ] 
 Making wide(r) memory from byte-wide memory? 
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Joined: Thu Aug 15, 2019 1:20 pm
Posts: 3
Hello,
Are there any good examples available on how to make wider memory when all you have connected to you FPGA hardware is byte-wide memory? I'm talking about static RAM, not block RAM or other memory bits inside a FPGA chip. I have searched a bit, but perhaps I'm using the wrong search words. I'm quite new to using FPGAs.

Background:
I am trying to adapt (port? not sure about terminology here) Project Oberon (http://www.projectoberon.com/) so it will run on Multicomp board, like this one https://www.retrobrewcomputers.org/doku ... ii-c:start
(Multicomp is Grant Searle's creation: http://searle.wales/).
Anyway, the Multicomp board has two AS6C4008 RAM chips connected to it, so that the data bus is 8-bit. And the RISC5 cpu in the computer that runs Project Oberon wants a 32-bit wide memory..
So I need a way to do that.
Not sure it will work out at all, the result might be too slow (reading 4 bytes in sequence rather than one 32-bit word) but it is fun to try.

Any help or pointers to places I can learn more is appreciated.

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Torfinn


Thu Dec 10, 2020 4:34 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1632
It certainly can be done. @hoglet here did it to run a more-than-byte-wide OPC cpu from the 8 bit wide RAM on an OHO GOP board. It turned out to be advantageous also to have a very small simple cache. See
https://github.com/revaldinho/opc/blob/ ... ntroller.v
and the surrounding machinery.


Thu Dec 10, 2020 4:52 pm

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1484
Location: Canada
I have put something similar together for the CS01 project. It interfaces an FPGA to a high speed static ram that is only eight bits wide. It runs only the memory cycles that needs to. The interface is to a 32-bit WISHBONE bus.

https://github.com/robfinch/CoresCS01/rtl/cs01memInterface.sv

An example of usage is in this file:
https://github.com/robfinch/CoresCS01/rtl/SoCCS01.sv

Note the interface was to 8 ns static ram so if interfacing to slow ram wait states will need to be inserted.

_________________
Robert Finch http://www.finitron.ca


Thu Dec 10, 2020 11:17 pm WWW

Joined: Thu Aug 15, 2019 1:20 pm
Posts: 3
BigEd wrote:
It certainly can be done. @hoglet here did it to run a more-than-byte-wide OPC cpu from the 8 bit wide RAM on an OHO GOP board. It turned out to be advantageous also to have a very small simple cache. See
https://github.com/revaldinho/opc/blob/ ... ntroller.v
and the surrounding machinery.


Thanks, I'll have a look and see if I can understand how it works.

_________________
Torfinn


Mon Dec 14, 2020 8:41 am

Joined: Thu Aug 15, 2019 1:20 pm
Posts: 3
robfinch wrote:
I have put something similar together for the CS01 project. It interfaces an FPGA to a high speed static ram that is only eight bits wide. It runs only the memory cycles that needs to. The interface is to a 32-bit WISHBONE bus.

https://github.com/robfinch/CoresCS01/rtl/cs01memInterface.sv

An example of usage is in this file:
https://github.com/robfinch/CoresCS01/rtl/SoCCS01.sv

Note the interface was to 8 ns static ram so if interfacing to slow ram wait states will need to be inserted.


This looks very useful - thanks!
Yes, the RAM chips on the Multicomp board are 55ns I think, so I'll keep that in mind.

_________________
Torfinn


Mon Dec 14, 2020 8:50 am
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