I was just reading through this fascinating but mostly over my head story of building a GPS receiver from scratch, and I see the author, Andrew Holme, uses a bespoke Forth CPU to perform some millisecond timescale tasks, freeing up FPGA fabric for the nanosecond timescale hardware engines.
http://www.aholme.co.uk/GPS/Main.htmIt's open source too, which is always nice.
http://www.aholme.co.uk/GPS/SRC/2013/Verilog/CPU.vIt's on a Spartan 3 FPGA, on a custom board:
Quote:
Features:
- FPGA resources: 360 slices + 2 BRAMs
- Single-cycle instruction execution
- FORTH-like, dual-stack architecture
- 32-bit stack and ALU data paths
- 64-bit double-precision operations
- Hardware multiplier
- 2k byte (expandable to 4k byte) code and data RAM
- Macro assembler code development
Quote:
Total code plus data size of the GPS application is less than 750 words, despite all loops being unrolled.
He links also to a previous project, the TTL-based Mark 1 Forth computer:
http://www.aholme.co.uk/Mk1/Architecture.htm
