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 Ben Eater's SAP inspired computer implemented in VHDL 
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Joined: Thu Aug 24, 2017 8:52 pm
Posts: 4
Hello! I have just recently discovered this forum and I thought some people here might find my latest simple FPGA project mildly interesting.

I have implemented a version of Ben Eater's SAP computer ( in VHDL for an FPGA (currently Lattice MachXO2-1200, but it should be easily portable). It is a very simple project, but might be useful for someone who wants to play around with a working implementation. It currently has only 8-bit binary GPIO "output", but it does include a TX only UART (9600 8N1) which produces a real-time "cycle trace" of the CPU (so you get a "log" showing internal CPU state for each cycle that is similar to looking at all the LEDs on Ben's breadboard implementation).

Mostly this project is educational, and eventually I hope to write an article describing the design to help people wrap their head around FPGA (and simple CPU) development.

Xark -

Thu Aug 24, 2017 9:23 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Welcome! An interesting project, for sure. Is there a block diagram anywhere, or a table showing the instruction format? Looks like a byte-wide two-register machine with perhaps single-byte instructions - but the details are where it gets interesting!

Fri Aug 25, 2017 7:55 am

Joined: Thu Aug 24, 2017 8:52 pm
Posts: 4
Hi Ed (love your OPC stuff),

No, this is strictly a toy 4-bit educational CPU (including 4-bit address bus) for TTL on a (large-ish) breadboard. The cool part are the many hours of amazing videos Ben has made showing exactly how he designed and built every single part of the computer and how it all works (all the way from "what is a semiconductor", what is a flip-flop etc.). The actual CPU design is very similar to the SAP-1 from an out of print computer book called Digital Computer Electronics.

I have attached a diagram of the CPU "screen grabbed" from Youtube to this post.

As far as the instruction set, high 4 bits is instruction and low 4 bits are operand (or ignored). Ben hasn't gotten to JCS yet (jump carry set), but here are the instructions plus that one:
   -- Ben Eater SAP inspired CPU instruction set:
   -- 0000 xxxx   NOP           no-operation
   -- 0001 mmmm   LDA M         A = RAM[M]
   -- 0010 mmmm   ADD M         A = A+RAM[M]
   -- 0011 mmmm   SUB M         A = A-RAM[M]
   -- 0100 mmmm   STA M         RAM[M] = A
   -- 0101 iiii   LDI N         A = N (4-LSB)
   -- 0110 mmmm   JMP M         PC = M
   -- 0111 mmmm   JCS M         if (carry) then PC = M
   -- 1000 xxxx   ??? (unused, acts like NOP)
   -- 1001 xxxx   ??? (unused, acts like NOP)
   -- 1010 xxxx   ??? (unused, acts like NOP)
   -- 1011 xxxx   ??? (unused, acts like NOP)
   -- 1100 xxxx   ??? (unused, acts like NOP)
   -- 1101 xxxx   ??? (unused, acts like NOP)
   -- 1110 xxxx   OUT            output A register
   -- 1111 xxxx   HLT            halt CPU clock (forces clock enable low)

SAP stands for "Simple As Possible" to teach about CPUs and digital electronics (and maybe a bit of FPGAs and VHDL with my project). Of course the first thing one wants to do when you get this operational is to extend it. Thankfully, this is a lot easier than re-wiring things on a breadboard.


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Fri Aug 25, 2017 9:18 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Thanks - 4 bits eh? Even simpler than I thought! But that's still a computer. I'm all for it.

Fri Aug 25, 2017 3:03 pm
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