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 clock division w/ CPLD 
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Joined: Mon Mar 05, 2018 6:28 pm
Posts: 2
I'm making a DRAM controller with an ATF1508, clocking it at 80 MHz, and was going to divide the clock in the CPLD to provide the CPU clock to a 68HC000.

Anyone know if the square wave coming out of the ATF1508 will be well-behaved, with a 50% duty cycle and reasonably sharp edges? I read reports that the 68HC000 can hit 40 MHz, so I wanted to see if I could get it up there, but I worry about whether I should just use a dedicated clock divider chip instead since the period would only be 25ns at 40 MHz

Thanks in advance,


Tue Mar 20, 2018 7:06 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Welcome! I think it's difficult to say how close to 50% duty cycle you might get - the ATF1508 CPLD has a propagation delay of 7ns max, which as an indicator of how long the internal delays might be is quite a high proportion of a 12.5ns phase. You should check the datasheet of the CPU to see what duty cycle tolerance it has - it might not care too much, if internally it only uses one edge, or it could be tightly specified.

In short, I don't know, but datasheets are your friend. Really you'd like a timing analyser for your design, but I'm not aware that such things exist.

Maybe someone more knowledgeable will be able to help.

Wed Mar 21, 2018 8:44 am

Joined: Mon Mar 05, 2018 6:28 pm
Posts: 2
I made the test rig, got distracted halfway through programming the CPLD, and picked it back up two years later.

So, the ATF1508 can emit fantastic clock signals, no issue there, looked great on the scope. But, at 80 MHz, the device did not behave like the simulator said it would. I had to stick in flip-flops in a few spots in the CUPL code (whenever something time sensitive was happening with a lot of combinatorial logic) or else the signals wouldn't propagate in time. WinCUPL has no facilities for estimating timing, so it was all guesswork until something worked. Also, WinCUPL crashes constantly for no damn reason, and won't even print error messages half the time you have a problem, just fail to produce a JEDEC file. It's a miserable piece of software.

Anyhow, the test harness has two selectable master clocks, an 80 MHz clock and a 64 MHz clock. These are divided down from 40 MHz, 20 MHz, and so on to 1 MHz, and from 32 MHz, 16 MHz, and so on to 1 MHz, depending on the master clock selection. A microcontroller and the ATF1508 work in tandem to put a small program in memory and output to the LED display via SPI.

I had a bunch of 68000 CPU's I picked up on aliexpress. Many of them were labelled "6800P12" and "6800P8", yes, 6800, not 68000. So clearly there is some remarking of the parts involved.

Testing found that the 68HC000's and the 68000's and the remarked "6800"'s all would run up to 16 MHz, regardless of the clock speed marked on the chip. The exception was a 68HC000P16 that wouldn't run above 8 MHz. One of the "6800"'s would work at 20 MHz for a few seconds before giving up. So, overclocking in this DIP64 package won't be happening with the 68HC000. I expect that the successful overclocking I read about was actually with a 68EC000 or 68SEC000.

Anyhow, here's a picture of the rig. The LED display on the right is the current clock speed, and the LED display on the left is used by the program that the 68000 runs to have one of the segments move in a circle around the display.

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Fri May 08, 2020 1:51 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Looks nice, and interesting results.

Just a note: it's normal when testing to apply some sort of margin of safety. If, for example, you decided to apply a 10% margin, you might test with a 4.5V supply, or test at 18MHz. Or maybe you could arrange to run the board at an elevated temperature.

That 20MHz almost-working: it is always OK from power-on for a little while? And it's running the same loop when it's working and then not working? I wonder if the part is warming up.

Fri May 08, 2020 6:08 am
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