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 [ 6 posts ] 
 Help/Critique for a design with an ATF1508 CPLD 
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Joined: Wed May 15, 2019 1:17 am
Posts: 25
Hi all, having finished a hardware project without a CPLD, I'm about to start on my first project with an ATF1508 CPLD. This forum seems to be quite active so I thought I'd ask for ideas, suggestions, feedback, critique here.

So the new design is a 6809 board with the CPLD doing address decoding and acting as an MMU. I have written the Verilog code in Quartus and tried pof2jed to turn the result into a format suitable for the ATF1508. I'll buy a new device on-line, so I won't need 12V for programming it (I hope).

But, questions ...

The OE1 line, should I tie it high, low or let it float? I don't have any tri-state CPLD outputs in my design.

I've seen mention of a Linux workflow which uses yosys to go Verilog -> EDIF netlist -> WinCUPL -> JEDEC file. Has anybody else tried this instead of the workflow through pof2jed?

I'm going to design the PCB to be a "hat" that sits on top of a Mega 2560 Arduino. I'll bring out most of the lines from the 6809, plus several of the spare CPLD lines. This will allow me to see/record the address/data/other lines. I might also wire a CPLD line out to the 6809 HALT line, so I can use the Arduino to single-step the CPU.

Question: has anybody used an Arduino to program an ATF1508?

Finally, while I've done some Verilog and digital logic design before, I'd be more than grateful if someone would cast their eyes over the design (mainly the CPLD section) and give some feedback, especially if I've made big mistakes. The project is at https://github.com/DoctorWkt/MMU09.

Many thanks in advance for any suggestions, Warren


Sun Aug 27, 2023 8:44 pm

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1789
Sounds great, and thanks for sharing and open-sourcing. I hope you've had a good look at the datasheet. There's always a lot to learn in a datasheet.
https://ww1.microchip.com/downloads/en/ ... oc1408.pdf

For sure you should tie off unused inputs. It looks to me like you probably don't need to worry about whether you tie off high or low, if you haven't got any tristate outputs, but I would tend to tie off active in this case, it's just less surprising that way.

The device seems to be in-system programmable with JTAG, so yes, should be quite possible to program with Arduino (or Raspberry Pi) - I see it's a 3V chip, but the datasheet says it will tolerate 5V inputs.


Mon Aug 28, 2023 8:37 am

Joined: Tue Feb 10, 2015 7:07 am
Posts: 52
DoctorWkt wrote:
The OE1 line, should I tie it high, low or let it float? I don't have any tri-state CPLD outputs in my design.

If you are not using OE1 as a global tristate control, then it doesn't matter what level it is tied to, as it's just an unused input.

There is a programmable pin-keeper circuit on each of the inputs and I/Os, which ensures unused pins do not float. So there is no need to explicitely tie unused pins to a defined logic level.
DoctorWkt wrote:
I've seen mention of a Linux workflow which uses yosys to go Verilog -> EDIF netlist -> WinCUPL -> JEDEC file. Has anybody else tried this instead of the workflow through pof2jed?

I put together that workflow a few months ago, but haven't yet used it in anger. If you try it out, please report do back.
DoctorWkt wrote:
Finally, while I've done some Verilog and digital logic design before, I'd be more than grateful if someone would cast their eyes over the design (mainly the CPLD section) and give some feedback, especially if I've made big mistakes. The project is at https://github.com/DoctorWkt/MMU09.

I didn't spot anything obviously wrong in the Verilog, and it looks a very interesting approach. I'm very much looking forward to seeing how this project develops.

Verilator came up with a couple of minor warnings:
Code:
$ verilator --lint-only mmu_decode.v
%Warning-INITIALDLY: mmu_decode.v:56:21: Delayed assignments (<=) in initial or final block
                                       : ... Suggest blocking assignments (=)
   56 |   initial kmodeflag <= 1'b1;
      |                     ^~
                     ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message.
%Warning-INITIALDLY: mmu_decode.v:134:22: Delayed assignments (<=) in initial or final block
                                        : ... Suggest blocking assignments (=)
  134 |   initial faultstate <= 2'b11;
      |                      ^~
%Error: Exiting due to 2 warning(s)

A couple of comments on things you might like to add:

1. A reset input, connected to the CPU reset signal, to reset the internal registers to a known state on reset.

2. Consider making the data bus read-write, so you can read back the page table entries. This would be useful for testing purposes.

3. If you have spare outputs, consider exposing as much of the internal state as you can, again for testing purposes.

Over the last year, BigEd, DominicBeesley, Revaldinho and myself have also been dabbling with some 6809/6309 SBC + MMU designs. We have a few paper designs (including one using the same CPLD), and one real design using 2x 22V10 PALs + 4x 74LS670. If you are interested in comparing notes, then I can post a few links.

Dave


Wed Aug 30, 2023 7:22 pm

Joined: Wed May 15, 2019 1:17 am
Posts: 25
hoglet wrote:
If you are not using OE1 as a global tristate control, then it doesn't matter what level it is tied to, as it's just an unused input.
There is a programmable pin-keeper circuit on each of the inputs and I/Os, which ensures unused pins do not float. So there is no need to explicitely tie unused pins to a defined logic level.


Thanks Dave. I see you used tri-state logic in your MMU design at https://github.com/hoglet67/atf15xx_yosys/blob/master/examples/mmu/mmu.v, so I guess I can do the same, in which case I should tie the OE1 line low.

hoglet wrote:
I put together that workflow a few months ago, but haven't yet used it in anger. If you try it out, please report do back.
I didn't spot anything obviously wrong in the Verilog, and it looks a very interesting approach. I'm very much looking forward to seeing how this project develops.
Verilator came up with a couple of minor warnings: ...


Thanks for that, I didn't realise verilator could lint. Yes, I plan on using your workflow to do this thing :D

hoglet wrote:
A couple of comments on things you might like to add:

1. A reset input, connected to the CPU reset signal, to reset the internal registers to a known state on reset.

2. Consider making the data bus read-write, so you can read back the page table entries. This would be useful for testing purposes.

3. If you have spare outputs, consider exposing as much of the internal state as you can, again for testing purposes.


I added the reset handling yesterday :) I should be able to add the logic to read the PTEs. Yes, I plan on taking all the spare CPLD lines, plus all the address/data/other signals out to pin headers which will plug into the Atmega 2560.

hoglet wrote:
Over the last year, BigEd, DominicBeesley, Revaldinho and myself have also been dabbling with some 6809/6309 SBC + MMU designs. We have a few paper designs (including one using the same CPLD), and one real design using 2x 22V10 PALs + 4x 74LS670. If you are interested in comparing notes, then I can post a few links.
Dave


Yes please! Thanks for your suggestions, Warren


Wed Aug 30, 2023 10:10 pm

Joined: Tue Feb 10, 2015 7:07 am
Posts: 52
DoctorWkt wrote:
hoglet wrote:
If you are interested in comparing notes, then I can post a few links.

Yes please! Thanks for your suggestions, Warren

OK, for general background see this thread: Adventures with the 6809 (and 6309).

There are currently two different board designs:
- one that fits on a 160mmx100mm 4-layer board and uses a ATF1508AS CPLD
- another that fits on a 100x100mm 4-layer board and uses two 22V10 PALs and four 74LS670

You can find schematics for both versions in github (on different branches):
https://github.com/hoglet67/SBC09/blob/ ... /sbc09.pdf
https://github.com/hoglet67/SBC09/blob/ ... /sbc09.pdf

So far, only the second of these has been built up:
Attachment:
image.jpg


In terms of software, we have two environments running:
- A version of BBC Basic 4
- A version of FUZIX

There is some further documention on the wiki:
https://github.com/hoglet67/SBC09/wiki

The MMU on the two PAL version is very simple, and supports either 8K or 16K blocks. There is no automatic switching between user and kernel modes, so the OS/Kernel must be mapped in at all time. In the case of the FUZIX port, this is the top 16KB block.

The MMU on the CPLD version should allow automatic switching between user and kernel mode, just like your MMU does. This is currently untested, and very likely will not work in it's current form. If you want to dig into the details, the latest Verilog is here. The CPLD also includes a SPI interface to speed up access to the SD Card.

The other thing that's worth noting is the 50-pin connector exposes a full bus interface.

I've used this for debugging, by connecting a cheap (£10) 16-bit USB logic analyzer to the following signals:
- DATA[7:0]
- RnW
- LIC
- BS
- BA
- ADDR[3:0]
- E (to the clock input)

The logic analyzer is set to capture on the falling edge of the E clock. I use a standalone program called the 6809 Protocol Decoder to convert the binary data back into a human readable instruction trace:
Code:
???? : B3 B3 B3       : RESET !!       : A=?? B=?? X=???? Y=???? U=???? S=???? DP=00 E=? F=1 H=? I=1 N=? Z=? V=? C=?
B3B4 : 31 8C E4       : LEAY $E4,PCR   : A=?? B=?? X=???? Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=? Z=0 V=? C=?
B3B7 : 7E 80 00       : JMP  $8000     : A=?? B=?? X=???? Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=? Z=0 V=? C=?
8000 : 7E BB 40       : JMP  $BB40     : A=?? B=?? X=???? Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=? Z=0 V=? C=?
BB40 : CC 00 34       : LDD  #$0034    : A=00 B=34 X=???? Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=?
BB43 : 8E FF 00       : LDX  #$FF00    : A=00 B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=?
BB46 : A7 01          : STA  $01,X     : A=00 B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=?
BB48 : A7 03          : STA  $03,X     : A=00 B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=?
BB4A : A7 84          : STA  ,X        : A=00 B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=?
BB4C : 43             : COMA           : A=FF B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=1
BB4D : A7 02          : STA  $02,X     : A=FF B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=1
BB4F : E7 01          : STB  $01,X     : A=FF B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=1
BB51 : E7 03          : STB  $03,X     : A=FF B=34 X=FF00 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=1
BB53 : 8E FF 20       : LDX  #$FF20    : A=FF B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=1
BB56 : 6F 01          : CLR  $01,X     : A=FF B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=0
BB58 : 6F 03          : CLR  $03,X     : A=FF B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=0
BB5A : 4A             : DECA           : A=FE B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=0
BB5B : A7 84          : STA  ,X        : A=FE B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=0
BB5D : 86 F8          : LDA  #$F8      : A=F8 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=0
BB5F : A7 02          : STA  $02,X     : A=F8 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=0
BB61 : E7 01          : STB  $01,X     : A=F8 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB63 : E7 03          : STB  $03,X     : A=F8 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB65 : 6F 84          : CLR  ,X        : A=F8 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=0
BB67 : 6F 02          : CLR  $02,X     : A=F8 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=1 V=0 C=0
BB69 : A6 02          : LDA  $02,X     : A=05 B=34 X=FF20 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB6B : 8E FF C0       : LDX  #$FFC0    : A=05 B=34 X=FFC0 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=1 Z=0 V=0 C=0
BB6E : C6 10          : LDB  #$10      : A=05 B=10 X=FFC0 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=10 X=FFC2 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=0F X=FFC2 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=0F X=FFC2 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=0F X=FFC4 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=0E X=FFC4 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=0E X=FFC4 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=0E X=FFC6 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=0D X=FFC6 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=0D X=FFC6 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=0D X=FFC8 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=0C X=FFC8 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=0C X=FFC8 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=0C X=FFCA Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=0B X=FFCA Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=0B X=FFCA Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=0B X=FFCC Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=0A X=FFCC Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=0A X=FFCC Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=0A X=FFCE Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB72 : 5A             : DECB           : A=05 B=09 X=FFCE Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB73 : 26 FB          : BNE  $BB70     : A=05 B=09 X=FFCE Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
BB70 : A7 81          : STA  ,X++      : A=05 B=09 X=FFD0 Y=B39B U=???? S=???? DP=00 E=? F=1 H=? I=1 N=0 Z=0 V=0 C=0
...

(this is actually a trace from a Dragon 32)

Dave


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Thu Aug 31, 2023 10:50 am

Joined: Wed May 15, 2019 1:17 am
Posts: 25
Dave, thanks for all those links to other projects. I'll definitely have a good look at them!

Status update: I've put up an archive of my current Kicad project on the Github page. I've also added the Icarus Verilog simulation of the whole SBC, which I'm using to ensure that the MMU actually works: https://github.com/DoctorWkt/MMU09.

The Verilog/Makefile also has a rule to use Dave's yosys workflow to make the JEDEC file for the CPLD.


Thu Aug 31, 2023 10:40 pm
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