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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 698
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Nov 1977 Byte Mag, has " Build a computer from scratch". It is a 8 bitter, 4 instructions In,Add,Store(negitive),Jump if Postitive. Ben.
Last edited by BigEd on Fri Nov 13, 2020 10:45 am, edited 1 time in total.
linkified
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| Fri Nov 13, 2020 10:29 am |
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B.Bibby
Joined: Tue Dec 18, 2018 11:25 am
Posts: 43
Location: Hampshire, UK.
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https://archive.org/details/byte-magazine-1977-11/page/n78/mode/1upIt is a very minimal instruction set, but neatly tackles the bootstrap problem with its WIO instruction. Code: ”WIO 00xxxxxx Wait for input to location N. Display current contents of location N while waiting.” Although entering a program by this method would be a little tedious, it seems good enough for entering a small secondary bootstrap. It is very similar to the method used in the CARDIAC paper computer. https://www.cs.drexel.edu/~bls96/museum/cardiac.html
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| Fri Nov 13, 2020 11:02 am |
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BigEd
Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1807
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I've a feeling the 1802 similarly supports a front panel bootstrap
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| Fri Nov 13, 2020 12:04 pm |
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monsonite
Joined: Mon Aug 14, 2017 8:23 am
Posts: 157
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Nice to see a bit of home-built TTL computing history.
However it had a chip-count of 35 ICs, of which 8 were the RAM.
The instruction set was very minimal - leaving a lot of scope for future improvements.
I would have thought that using a pair of 74181s as the ALU would have encouraged a more diverse instruction set.
In the author's defense - it was his first electronic project, and he learnt a lot about TTL design from the exercise - and he got an article published in BYTE !
Last edited by monsonite on Thu Apr 01, 2021 11:51 am, edited 1 time in total.
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| Fri Nov 13, 2020 12:32 pm |
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B.Bibby
Joined: Tue Dec 18, 2018 11:25 am
Posts: 43
Location: Hampshire, UK.
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| Thu Apr 01, 2021 10:04 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 698
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Turing Machine's while not practical, could also be considered one, depending on you view the state table and tape memory. They also look nice in mechanical form. Wooden https://hackaday.com/2018/03/08/mechani ... g-machine/https://www.youtube.com/watch?v=vo8izCKHiF0Taditional https://www.youtube.com/watch?v=E3keLeMwfHY
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| Sat Apr 03, 2021 4:58 am |
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Dr Jefyll
Joined: Tue Jan 15, 2013 5:43 am
Posts: 189
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B.Bibby wrote: Dr Jefyll’s MISC gets another mention on Hackaday. Thanks for that, B.Bibby. Sorry I've been slow to notice your post. I need to visit Anycpu.org more often! Also belonging on the MISC list are three offerings from Myron Plichota: -- Jeff
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| Sun Oct 31, 2021 2:32 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am
Posts: 698
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Here is my idea for a Minimal Instruction Set CPU, compared to my current CISC design. Added indirection (I) do I don't have self modifiying code. Code: A bit better move machine?
see: The Ultimate RISC
https://homepage.cs.uiowa.edu/~jones/arch/risc/
RISC
256K words of memory
62 PIN BUSS?
20 bit ALU 74LSXXX devices
1 us static memory cycle ~ summer 1976
4 uS for memory operation
3 uS for jump condition
+1 us for indirection
run is true
FF:NN:NNNN:NNNN:NNNN:NNNN word #1 from
FF
00 read word N
01 special decode read word N
10 read word N indirect
11 read byte N indirect , Sign is odd/even data
normal decode
FF:NN:NNNN:NNNN:NNNN:NNNN word #2 to
00 write word N
01 write word N and halt
10 write word N indirect
11 write byte N indirect , Sign is odd/even data
display i/o bus
special decode
FF:NN:NNNN:NNNN:NNNN:NNNN word #2 to
00 write word N decrimented
01 write word N incrimented
10 jmp if zero N (constant data) write swr
11 jmp if zero N indirect write swr
display i/o bus
PANEL run is false
00 idle read swr display mar
01 address read swr display mar
10 examine read pc++ display data in
11 deposit write pc++, swr display data in
MEMORY MAPPED DEVICES
3FFFx swr read only
3FFEX alu func write
0011 add
0111 sub
nnnn alu logic function 74181
active high data
0Inn read logic condition
1ss0 read acc left shift
1ss1 read acc right shift
111- read acc
3FFYX Y=7..0 I/O devices
30000 to 3FEFF ROM of some kind
MOVE-IT CARD
DATA PATH ~ 30 MSI LS CHIPS
STATE LOGIC ~ 4 CHIPS
DECODE ~ 7? CHIPS
TOTAL 41 CHIPS
ALU CARD
DATA PATH 74LS181 ~ 25 MSI CHIPS
DECODE ~ 10 CHIPS?
TOTAL 35 CHIPS
-----------------------------------------------------------------
CURRENT 20 BIT MACHINE
CISC
16 REGISTERS
ADDRESSING MODES
+-R,R+-@
DIRECT,INDEXED
20 BITS DEC 20 2021
0987 6543 2109 8765 4321
+------------------------+
|COOO:AAAA:000B:XXXX:----| R INDEXED/DIRECT
+------------------------+
|####:####:####:####:####| OFFSET
+------------------------+
+------------------------+
|COOO:AAAA:0010:XXXX:----| REG% / LEA
+------------------------+
+------------------------+
|-RSS:AAAA:0011:--##:####| SHIFT #-N
+------------------------+
+------------------------+
|COOO:AAAA:10YB:XXXX:####| R+
+------------------------+
+------------------------+
|IOOO:AAAA:01Y1:XXXX:####| BCC,JMP R+ / JSR R+
+------------------------+
+------------------------+
|IOOO:AAAA:0100:----:####| SCC #
+------------------------+
+------------------------+
|I111:AAAA:01Y0:XXXX:####| RETI
+------------------------+
+------------------------+
|COOO:AAAA:11+#:####:####| OP. R # SHORT IMMEDATE
+------------------------+
+------------------------+
|-111:AAAA:1100:00CC:0000| CTL A
+------------------------+
0 ADD A I
1 SUB B J
2 CAD C K
3 OR D S
4 XOR E W
5 AND F X
6 LD G Y
7 ST H Z
100 PIN BUS (S-100 STYLE)
CORE MEMORY CYCLE
ALU 2901'S
CONTROL SECTION
~ 15 MSI CHIPS FOR RANDOM LOGIC
2 256 X 8 PROMS OR 22V10'S
4 FPGA'S (82S100'S) OR 22V10'S
TOTAL 22 CHIPS
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| Tue Dec 21, 2021 4:28 am |
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