1985 to 2000 was a very fertile period for the development of specialised stack machine cpus that would execute Forth primitives directly.

Summarised in Phil Koopman's 1989 book "Stack Computers the New Wave" - this was a whole new unexplored territory for very fast processing engines.

https://users.ece.cmu.edu/~koopman/stac ... s_book.pdf

Beginning in 1985 with the Novix NC4016, then Chuck Moore's MuP21, ShBoom, iTV and the F21 developed in conjunction with Jeff Fox - this was the golden age - that promised us 500 Forth MIPS and workstation class processing power.

Some 25 years on, and these radical processor developments are little more than a fading memory - captured for posterity on the late Jeff Fox's UltraTechnology site. If you wish to spend a quiet Sunday afternoon reading about the heyday of budget cpu design - then Jeff's site will keep you occupied for hours.

Why do we not have 500MIP Forth engines for under a dollar these days? Why is it that some of these great ideas never made commercial reality?

Some clues are revealed within the archive or articles of UltraTechnology.

I guide you first to a publication from 25 years ago, produced by well known Forth guru Dr Chen Hanson Ting - who invested in the MuP21 "More on Forth Engines" is a fascinating potted history of the period - including Chuck's own OKAD - a self written tool for developing VLSI architectures.

http://www.ultratechnology.com/mofe16.htm

Now we have FPGAs and hardware description languages that make developing hardware so much easier. Is it not time to revisit some of these lost works, and with open source tools an a $5 FPGA forge on from the point where the first generation of Forth Wrights left of?

James Bowman's J1 Forth processor is very close in architecture to the original Novix 4016 and could serve as a starting point for investigation. The J1 benefits from on chip stacks which was not an option on the NC4016 gate array - and modern FPGA will give a 10X improvement in execution speed.

With the new ARTY Zynq FPGA board available for about $149 - hardware has never been so cheap

http://store.digilentinc.com/arty-z7-ap ... hobbyists/

For just around $50 you have access to several FPGA boards based around the Lattice 40 and it's recently reverse engineered open source tool chain.

Perhaps some enterprising Forther will take up the challenge to code the MuP21 or F21 into verilog and run it on a low cost FPGA board? Here's hoping.

A Merry Christmas and Prosperous New Year to all.



Ken Boak

You even can get FPGA boards below US$10.
—▶ http://gnarlygrey.atspace.cc/development-platform.html#upduino

Icestorm is starting to support them.
—▶ https://github.com/cliffordwolf/icestorm/issues/68

PSC1000 anybody,
ordered a couple from a very nice lady at Patriot Scientific, about 15 years ago, interesting byte code
machine instsructions, with microloops allowed within a 32bit word, capable of 200 M/bytes, yes bytes
pers/sec. Java freaks should feel well at home.Only had mine runing @ 80 Mhz with 15ns memory, but
but fast, so why can't this be done in Fpga.
Any comments.
I live in hope there are still inspired people out there.

Best Regards to all
Ian Hughes

Ian & List,

Interesting to hear of your experience with the PSC1000. Of all the cpus Chuck Moore worked on, this one and the Novix were possibly the only two that made a commercial appearance.

There is a list of soft cores intended to run Forth here http://www.forth.org/cores.html

Some of the links are broken, but of much interest is C.H Ting's fully documented eP16 - a complete Forth system running on a Lattice FPGA. Described in a nearly 200 page PDF, including all VHDL source code, and Ting's own eForth crafted to run on this core. There is a 1.78Mbyte zip as a download.

Ting adapted the design for different wordlengths - there was an eP8, eP16 and eP32.

The eP16 seems to be about the best fit for readily available 16-bit 10nS SRAM, and keeps the pin-out to what can be achieved sensibly in a LQFP package, without having to resort to BGA devices.

Ting worked with Chuck Moore on the MuP21 around 1990 - and many of the features of the MuP21 and the F21 core have been included in Ting's simplified eP16. It packs three, 5-bit instructions into a 16-bit word - so that the RAM is accessed at a reasonable rate. This also forms a natural pipeline allowing the cpu to execute an instruction every cycle.

This would be a good starting point for a FPGA stack machine - running at around 50MHz (possibly more) on a low cost FPGA.

Whilst the source is in VHDL, I'm going to look into a port to Verilog - making it accessible for the open source tools now available for the Lattice ICE 40 range of $5 FPGAs. - Clifford Wolf's Project Icestorm

Ting released an early source to the SVFiG back in 2000 - documented here. Whilst I have only elementary knowledge of VHDL - the description of the cpu architecture, instruction set and the VHDL source code is quite readable.

http://www.ultratechnology.com/p16vhdl.htm

More Forth chips on Jeff Fox's Ultratechnology site http://www.ultratechnology.com/chips.htm

http://www.clifford.at/icestorm/


Seasons Greetings to All


Ken