I've an idea for register renaming that doesn't use a physical register file. It uses the reorder buffer + architectural register file instead.
Could this work is what I'm wondering ?

Is the reorder buffer like an indirect register, like PIC's FSR, the INDF accesses the register pointed to by FSR? Or maybe instead like an index register, an offset in the register file?

The reorder buffer and register renaming I refer to is one used by a superscalar processor.



Register renaming is a bit like the FSR. Instead of a single FSR register though, there is a mapping table that maps the registers to other "physical registers". In the mapping table there are entries like "R1=R64" which tells the processor to use R64 whenever it sees R1 specified. There are more physical registers than there are logical (architectural) ones. Remapping the registers allows dependencies to be overcome.

What I think can be done is instead of using more physical registers, the mapping table can contain tags to destination results that are contained in the reorder buffer. So my mapping table contains entries like "R1=TAG1" rather than another physical register. The processor then gets the value for R1 from the reorder buffer entry containing the destination tag "TAG1". Eventually when the instruction is finished the map is reset so "R1=R1".

The reorder buffer itself is much larger than a register. It is a circular buffer that contains a number of entries. It's a little bit like a ring buffer of IR's that allows instructions to be queued up. Each entry contains an instruction, operands, the result of the instruction, and other bookkeeping fields.
While the processor is running, fetched instructions are stored in the tail positions of the reorder buffer. Instructions that are finished drop off the head of the buffer.