Having just bought a cheap Chromebook, I was looking into what CPU it has and what it looks like from a microarchitecture perspective, and found some resources which might be of interest. It seems that a few technical blogs go into quite a bit of detail when Intel announce something new. Most interesting, they compare the latest offering with the previous, and talk about what advantage comes from each change.

A microarchitecture wiki (mostly Intel):


Writeup from Anandtech.

Writeup from Real World Tech.

BigEd:

Thanks for the links. Interesting changes happening to all of the micro-architectures. There appears to be a continuing effort to simplify the basic architecture and reduce the pipeline depths. The corresponding decrease in the branch mis-prediction penalties is an interesting side-effect of the decrease in the pipeline depth and continuing improvements in the branch predictors.

Side-effect, Michael? That's an odd way of putting it. Surely the decrease in mis-prediction penalties is what motivated the shorter pipeline and improved branch predictors!

Perhaps I should have said that the reduction in the mis-prediction penalty is a side-effect of the re-organized pipeline that results from the shift to Out of Order (OoO) execution. The re-organized pipeline allows the branch prediction logic to bypass three pipeline stages in the event that a memory operand is not required. That change reduces the effective mis-prediction penalty from 13 cycles to 10 cycles. (see the Anandtech article linked by BigEd)

There is an improvement in the branch predictor, but the improvement is linked to increases in the depth/size of the branch predictor memories. Without changes to the pipeline, the mis-prediction penalty remains the same. With the additional depth to the branch prediction tables/memories, the efficiency of the branch predictor improves considerably. Apparently, the reduction in feature size allows the addition of a second branch predictor which uses a different algorithm. One branch predictor works over the instruction fetch pipeline stages, and the other over the instruction decode pipeline stages.

Did some reading on the subject of branch prediction last night. It's an interesting subject.

Somewhat related, this tabulation of many CPUs running a compression/decompression benchmark has links describing the cache hierarchy of each, with sundry other microarchitectural details:
http://www.7-cpu.com/

On the topic of microarchitectural details and comparisons, here's RealWorldTech from 2002 on the last Alpha and the second Itanium:
http://www.realworldtech.com/ev8-mckinley/
"These two remarkable processor designs are, in many ways, studies in contrast. They differ starkly in instruction set architecture design philosophy, implementation philosophy, process technology, their stage in the development cycle, and their ultimate destiny."

Here's the EV8:



and here's McKinley:




And from 1999, here's a preview of Merced, the 1st Itanium, from the same site. With this:

and this:

Fascinating reading. I especially like the diagrams. It's amazing how much has changed, and how much has stayed the same since the early 2000's. I wonder how much the logic will change versus the implementation technology in the future.

I do like to see diagrams with the clock boundaries visible - sometimes it's as useful to know when something is happening as to know what it is that's happening.