Last visit was: Wed Dec 01, 2021 6:03 pm
It is currently Wed Dec 01, 2021 6:03 pm



 [ 33 posts ]  Go to page Previous  1, 2, 3
 Noc - Network on chip 
Author Message

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
Work was done on improving software for the grid computer. A common set of code is now contained in the file Node.asm. This file contains the receiver dispatch code and a standard set of message handlers. The receiver dispatches to different command handlers for each device in the node based on the message destination.

Rather than have a custom set of messages for each device in the grid (the way it was coded for simplicity in the beginning), a more or less standard set of device driver messages was setup. Some software structure was borrowed from other projects.

A routine was written to enumerate the devices in the grid. This enumeration is done on reset and displays the available devices as the system boots. Doesn’t work yet. Well that’s what it’s supposed to do, but I’m waiting for the system to build with a software fix.

The format of the messages sent around the network has changed. While writing device drivers I noted it would be handy if the device ID could be transmitted in the message as part of the source / destination. So it was added, this made the message ID fields 16 bits in size with the format {D,X,Y,Z} where ‘D’ is a nybble for the device ID on a node. There are unlikely to be more than 15 devices on a single node. The most there are right now is three. Device ‘0’ represents the node itself. So $1211 is device one (keyboard) on node $211.

_________________
Robert Finch http://www.finitron.ca


Thu Jun 29, 2017 4:53 am WWW

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1531
Location: Canada
I’m planning on developing a network-on-chip again but this time I’d like to use a standard processing core that has more software available for it. I’d like to use a BASIC interpreter in a master / slave fashion to control the nodes.

The processing core for a network node has to be fairly small as resources per node are limited. That means an 8 or 16 bit cpu. At the same time overall network resources are much larger and it’s desirable to access them easily. So a core would be a 16 bit cpu with a 32 bit address bus, sounds like a 68000? eh.

The problem with using the 68k system as a base is complexity. Something like the Amiga or AtariST has complex graphics and audio hardware. So one thought is to use a standard older 8 bit system as a base to build on. Another thought is to use a 6809 core with possibly coco3 compatibility for I/O.
I’ve yet to decide. But putting together all the software for a custom processor (like the Butterfly) is just too big of a chore.

_________________
Robert Finch http://www.finitron.ca


Mon Nov 20, 2017 3:10 pm WWW

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1647
Yes, it turns out software is the bigger part of the problem! I think 6502 is the smallest core, and there are Basics for it, so all you need - for any 8 bit core - is some scheme for banking memory. I would say 68k is only a win if you've lots of space and really want compiled code. Even then, z80 would probably be a better bet.


Mon Nov 20, 2017 4:13 pm
 [ 33 posts ]  Go to page Previous  1, 2, 3

Who is online

Users browsing this forum: CCBot and 0 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software